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authorJiong Wang <jiong.wang@arm.com>2015-01-13 11:18:10 +0000
committerJiong Wang <jiong.wang@arm.com>2015-01-13 11:18:10 +0000
commitbab91cce20e052822e128c672e0570c8f3f58131 (patch)
treeaff1fe248016ea56a47272fa83b994f62806c9e0 /bfd
parent92fc2e6978d9a7c8324c7e851dbee59e22ec7a37 (diff)
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[AArch64] Enable overflow check for R_AARCH64_TLSLE_ADD_TPREL_HI12
bfd/ PR ld/17415 * elfnn-aarch64.c (elfNN_aarch64_howto_table): Mark R_AARCH64_TLSLE_ADD_TPREL_HI12 as complain_overflow_unsigned. * elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Correct the bit mask. ld/testsuite/ PR ld/17415 * ld-aarch64/pr17415.s: Source file for new test. * ld-aarch64/pr17415.d: Expect file for new test. * ld-aarch64/aarch64-elf.exp: Run the new test.
Diffstat (limited to 'bfd')
-rw-r--r--bfd/ChangeLog8
-rw-r--r--bfd/elfnn-aarch64.c2
-rw-r--r--bfd/elfxx-aarch64.c4
3 files changed, 12 insertions, 2 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index a3e1d8f..e7630ab 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,11 @@
+2015-01-13 Jiong Wang <jiong.wang@arm.com>
+
+ PR ld/17415
+ * elfnn-aarch64.c (elfNN_aarch64_howto_table): Mark
+ R_AARCH64_TLSLE_ADD_TPREL_HI12 as complain_overflow_unsigned.
+ * elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Correct the
+ bit mask.
+
2015-01-12 Terry Guo <terry.guo@arm.com>
* elflink.c (_bfd_elf_gc_mark_debug_special_section_group): New
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index 3554a87..f632eee 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -1038,7 +1038,7 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
12, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
- complain_overflow_dont, /* complain_on_overflow */
+ complain_overflow_unsigned, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (TLSLE_ADD_TPREL_HI12), /* name */
FALSE, /* partial_inplace */
diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c
index 54b69fd..25a6228 100644
--- a/bfd/elfxx-aarch64.c
+++ b/bfd/elfxx-aarch64.c
@@ -450,7 +450,9 @@ _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
value = (value + addend) & (bfd_vma) 0xffff0000;
break;
case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
- value = (value + addend) & (bfd_vma) 0xfff000;
+ /* Mask off low 12bits, keep all other high bits, so that the later
+ generic code could check whehter there is overflow. */
+ value = (value + addend) & ~(bfd_vma) 0xfff;
break;
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0: