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| author | Jiawei <jiawei@iscas.ac.cn> | 2024-02-28 16:27:17 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-03-08 10:04:25 +0800 |
| commit | dac0b8a4af48e1c5739a19cd5501c7a81bc44ab0 (patch) | |
| tree | 227d87a28af1ea66c635a72e0252864c18502d6b /bfd | |
| parent | acab5b12b9765d856d8618c11e4f54115396fda7 (diff) | |
| download | gdb-dac0b8a4af48e1c5739a19cd5501c7a81bc44ab0.zip gdb-dac0b8a4af48e1c5739a19cd5501c7a81bc44ab0.tar.gz gdb-dac0b8a4af48e1c5739a19cd5501c7a81bc44ab0.tar.bz2 | |
RISC-V: Support Zabha extension.
The Zabha extension[1] supports for byte and halfword
atomic memory operations. This patch add all instructions
include in Zabha. Further work is waiting Zacas[2] merge.
[1] https://github.com/riscv/riscv-zabha/tags
[2] https://sourceware.org/pipermail/binutils/2023-May/127700.html
Version log:
Add new imply relation that Zabha extension implies A extension.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): New imply.
(riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* testsuite/gas/riscv/zabha-32.d: New test.
* testsuite/gas/riscv/zabha.d: New test.
* testsuite/gas/riscv/zabha.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes.
(MASK_AMOADD_B): Ditto.
(MATCH_AMOXOR_B): Ditto.
(MASK_AMOXOR_B): Ditto.
(MATCH_AMOOR_B): Ditto.
(MASK_AMOOR_B): Ditto.
(MATCH_AMOAND_B): Ditto.
(MASK_AMOAND_B): Ditto.
(MATCH_AMOMIN_B): Ditto.
(MASK_AMOMIN_B): Ditto.
(MATCH_AMOMAX_B): Ditto.
(MASK_AMOMAX_B): Ditto.
(MATCH_AMOMINU_B): Ditto.
(MASK_AMOMINU_B): Ditto.
(MATCH_AMOMAXU_B): Ditto.
(MASK_AMOMAXU_B): Ditto.
(MATCH_AMOSWAP_B): Ditto.
(MASK_AMOSWAP_B): Ditto.
(MATCH_AMOADD_H): Ditto.
(MASK_AMOADD_H): Ditto.
(MATCH_AMOXOR_H): Ditto.
(MASK_AMOXOR_H): Ditto.
(MATCH_AMOOR_H): Ditto.
(MASK_AMOOR_H): Ditto.
(MATCH_AMOAND_H): Ditto.
(MASK_AMOAND_H): Ditto.
(MATCH_AMOMIN_H): Ditto.
(MASK_AMOMIN_H): Ditto.
(MATCH_AMOMAX_H): Ditto.
(MASK_AMOMAX_H): Ditto.
(MATCH_AMOMINU_H): Ditto.
(MASK_AMOMINU_H): Ditto.
(MATCH_AMOMAXU_H): Ditto.
(MASK_AMOMAXU_H): Ditto.
(MATCH_AMOSWAP_H): Ditto.
(MASK_AMOSWAP_H): Ditto.
(DECLARE_INSN): New declare.
* opcode/riscv.h (enum riscv_insn_class): New class.
opcodes/ChangeLog:
* riscv-opc.c: New instructions.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index a4aa71f..7313666 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1191,6 +1191,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, + {"zabha", "a", check_implicit_always}, {"zvfh", "zvfhmin", check_implicit_always}, {"zvfh", "zfhmin", check_implicit_always}, {"zvfhmin", "zve32f", check_implicit_always}, @@ -1347,6 +1348,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2510,6 +2512,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zmmul"); case INSN_CLASS_A: return riscv_subset_supports (rps, "a"); + case INSN_CLASS_ZABHA: + return riscv_subset_supports (rps, "zabha"); case INSN_CLASS_ZAWRS: return riscv_subset_supports (rps, "zawrs"); case INSN_CLASS_F: @@ -2732,6 +2736,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _ ("m' or `zmmul"); case INSN_CLASS_A: return "a"; + case INSN_CLASS_ZABHA: + return "zabha"; case INSN_CLASS_ZAWRS: return "zawrs"; case INSN_CLASS_F: |