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| author | Mary Bennett <mary.bennett682@gmail.com> | 2024-08-30 04:46:58 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-09-03 12:02:28 +0800 |
| commit | a6ecb18b796b2a7342ab72d14c6bd440b718030f (patch) | |
| tree | 20e4c5d6e37710ccdd16d74428be66f4e3e612f4 /bfd | |
| parent | cf525621820060a5c77efa153e6d2ec6a5ad47c9 (diff) | |
| download | gdb-a6ecb18b796b2a7342ab72d14c6bd440b718030f.zip gdb-a6ecb18b796b2a7342ab72d14c6bd440b718030f.tar.gz gdb-a6ecb18b796b2a7342ab72d14c6bd440b718030f.tar.bz2 | |
RISC-V: Add support for XCVsimd extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett682@gmail.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* NEWS: Updated.
* config/tc-riscv.c (validate_riscv_insn): Add custom operands.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Note XCVsimd as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/march-help.l: Add xcvsimd.
* testsuite/gas/riscv/x-cv-simd.d: New test.
* testsuite/gas/riscv/x-cv-simd.s: New test.
* testsuite/gas/riscv/x-cv-simd-fail.d: New test.
* testsuite/gas/riscv/x-cv-simd-fail.l: New test.
* testsuite/gas/riscv/x-cv-simd-fail.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK macros
for XCVsimd.
* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
for XCVsimd.
(enum riscv_insn_class): Add the XCVsimd instruction class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add custom operands.
* riscv-opc.c: Add XCVsimd instructions.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index d517b2e..64b7d71 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1472,6 +1472,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xcvmem", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xcvsimd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2734,6 +2735,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xcvmac"); case INSN_CLASS_XCVMEM: return riscv_subset_supports (rps, "xcvmem"); + case INSN_CLASS_XCVSIMD: + return riscv_subset_supports (rps, "xcvsimd"); case INSN_CLASS_XTHEADBA: return riscv_subset_supports (rps, "xtheadba"); case INSN_CLASS_XTHEADBB: @@ -3014,6 +3017,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xcvmac"; case INSN_CLASS_XCVMEM: return "xcvmem"; + case INSN_CLASS_XCVSIMD: + return "xcvsimd"; case INSN_CLASS_XTHEADBA: return "xtheadba"; case INSN_CLASS_XTHEADBB: |