Add MIPS r3 and r5 support.

This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5.  Secondly it adds support for the eretnc instruction.

ChangeLog:

bfd/
	* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
	mips32r5 and mips64r5.
	* archures.c (bfd_architecture): Likewise.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (arch_info_struct): Likewise.
	* elfxx-mips.c (mips_set_isa_flags): Likewise.

gas/
	* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
	and mips64r5.
	(ISA_HAS_64BIT_FPRS): Likewise.
	(ISA_HAS_ROR): Likewise.
	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
	(ISA_HAS_MXHC1): Likewise.
	(hilo_interlocks): Likewise.
	(md_longopts): Likewise.
	(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
	(ISA_HAS_DROR): Likewise.
	(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
	OPTION_MIPS64R5.
	(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(md_parse_option): Likewise.
	(s_mipsset): Likewise.
	(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
	and mips64r5.  Also change p5600 entry to be mips32r5.
	* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	* configure: Regenerate.
	* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
	-mips64r5 command line options.
	* doc/as.texinfo: Likewise.

gas/testsuite/
	* gas/mips/mips.exp: Add MIPS32r5 tests.  Also add the mips32r3,
	mips32r5, mips64r3 and mips64r5 isas to the testsuite.
	* gas/mips/r5.s: New test.
	* gas/mips/r5.d: Likewise.

include/opcode/
	* mips.h (INSN_ISA_MASK): Updated.
	(INSN_ISA32R3): New define.
	(INSN_ISA32R5): New define.
	(INSN_ISA64R3): New define.
	(INSN_ISA64R5): New define.
	(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
	INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
	(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(INSN_UPTO32R3): New define.
	(INSN_UPTO32R5): New define.
	(INSN_UPTO64R3): New define.
	(INSN_UPTO64R5): New define.
	(ISA_MIPS32R3): New define.
	(ISA_MIPS32R5): New define.
	(ISA_MIPS64R3): New define.
	(ISA_MIPS64R5): New define.
	(CPU_MIPS32R3): New define.
	(CPU_MIPS32R5): New define.
	(CPU_MIPS64R3): New define.
	(CPU_MIPS64R5): New define.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
	(I34): New define.
	(I36): New define.
	(I66): New define.
	(I68): New define.
	* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(parse_mips_dis_option): Update MSA and virtualization support to
	allow mips64r3 and mips64r5.

6 files changed, 33 insertions, 0 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 902dc73..fd62c28 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,12 @@
+2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
+	mips32r5 and mips64r5.
+	* archures.c (bfd_architecture): Likewise.
+	* bfd-in2.h (bfd_architecture): Likewise.
+	* cpu-mips.c (arch_info_struct): Likewise.
+	* elfxx-mips.c (mips_set_isa_flags): Likewise.
+
 2014-05-06  Richard Sandiford  <rdsandiford@googlemail.com>
 
 	* elfxx-mips.h (elfxx-mips.h): Declare.
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index 4f99c47..79abe42 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -791,9 +791,13 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
 	case bfd_mach_mips16:
 	case bfd_mach_mipsisa32:
 	case bfd_mach_mipsisa32r2:
+	case bfd_mach_mipsisa32r3:
+	case bfd_mach_mipsisa32r5:
 	case bfd_mach_mips5:
 	case bfd_mach_mipsisa64:
 	case bfd_mach_mipsisa64r2:
+	case bfd_mach_mipsisa64r3:
+	case bfd_mach_mipsisa64r5:
 	case bfd_mach_mips_sb1:
 	case bfd_mach_mips_xlr:
 	  /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
diff --git a/bfd/archures.c b/bfd/archures.c
index 4ab5f1d..9b47504 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -182,8 +182,12 @@ DESCRIPTION
 .#define bfd_mach_mips_xlr              887682   {* decimal 'XLR'  *}
 .#define bfd_mach_mipsisa32             32
 .#define bfd_mach_mipsisa32r2           33
+.#define bfd_mach_mipsisa32r3           34
+.#define bfd_mach_mipsisa32r5           36
 .#define bfd_mach_mipsisa64             64
 .#define bfd_mach_mipsisa64r2           65
+.#define bfd_mach_mipsisa64r3           66
+.#define bfd_mach_mipsisa64r5           68
 .#define bfd_mach_mips_micromips        96
 .  bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_intel_syntax	(1 << 0)
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index e38441c..8b7f2ee 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1967,8 +1967,12 @@ enum bfd_architecture
 #define bfd_mach_mips_xlr              887682   /* decimal 'XLR'  */
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33
+#define bfd_mach_mipsisa32r3           34
+#define bfd_mach_mipsisa32r5           36
 #define bfd_mach_mipsisa64             64
 #define bfd_mach_mipsisa64r2           65
+#define bfd_mach_mipsisa64r3           66
+#define bfd_mach_mipsisa64r5           68
 #define bfd_mach_mips_micromips        96
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_intel_syntax     (1 << 0)
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 6e5a787..360049c 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -87,8 +87,12 @@ enum
   I_mips5,
   I_mipsisa32,
   I_mipsisa32r2,
+  I_mipsisa32r3,
+  I_mipsisa32r5,
   I_mipsisa64,
   I_mipsisa64r2,
+  I_mipsisa64r3,
+  I_mipsisa64r5,
   I_sb1,
   I_loongson_2e,
   I_loongson_2f,
@@ -131,8 +135,12 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips5,    "mips:mips5",     FALSE, NN(I_mips5)),
   N (32, 32, bfd_mach_mipsisa32,  "mips:isa32",   FALSE, NN(I_mipsisa32)),
   N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
+  N (32, 32, bfd_mach_mipsisa32r3,"mips:isa32r3", FALSE, NN(I_mipsisa32r3)),
+  N (32, 32, bfd_mach_mipsisa32r5,"mips:isa32r5", FALSE, NN(I_mipsisa32r5)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
+  N (64, 64, bfd_mach_mipsisa64r3,"mips:isa64r3", FALSE, NN(I_mipsisa64r3)),
+  N (64, 64, bfd_mach_mipsisa64r5,"mips:isa64r5", FALSE, NN(I_mipsisa64r5)),
   N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, NN(I_sb1)),
   N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e",       FALSE, NN(I_loongson_2e)),
   N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",       FALSE, NN(I_loongson_2f)),
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index f8c1e64..49da874 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -11664,10 +11664,14 @@ mips_set_isa_flags (bfd *abfd)
       break;
 
     case bfd_mach_mipsisa32r2:
+    case bfd_mach_mipsisa32r3:
+    case bfd_mach_mipsisa32r5:
       val = E_MIPS_ARCH_32R2;
       break;
 
     case bfd_mach_mipsisa64r2:
+    case bfd_mach_mipsisa64r3:
+    case bfd_mach_mipsisa64r5:
       val = E_MIPS_ARCH_64R2;
       break;
     }