bfd:

	Add ms2.
	* archures.c (bfd_mach_ms2): Define.
	* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
	* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
	(ms1_elf_merge_private_bfd_data): Remove unused variables.  Add
	correct merging logic, with workaround.
	(ms1_elf_print_private_bfd_data): Add ms2 case.
	* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.

cpu:
	Add ms2
	* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
	model.
	(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
	f-cb2incr, f-rc3): New fields.
	(LOOP): New instruction.
	(JAL-HAZARD): New hazard.
	(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
	New operands.
	(mul, muli, dbnz, iflush): Enable for ms2
	(jal, reti): Has JAL-HAZARD.
	(ldctxt, ldfb, stfb): Only ms1.
	(fbcb): Only ms1,ms1-003.
	(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
	fbcbincrs, mfbcbincrs): Enable for ms2.
	(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
	* ms1.opc (parse_loopsize): New.
	(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
	(print_pcrel): New.

gas:
	Add ms2.
	* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
	(ms1_architectures): Add ms2.
	(md_parse_option): Add ms2.
	(md_show_usage): Add ms2.
	(md_assemble): Add JAL_HAZARD detection logic.
	(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
	* doc/c-ms1.texi: New.
	* doc/all.texi: Add MS1.
	* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
	* doc/Makefile.in: Rebuilt.
	* doc/Makefile: Rebuilt.

gas/testsuite:
	Add ms2.
	* gas/ms1/allinsn.d: Adjust pcrel disassembly.
	* gas/ms1/errors.exp: Fix target triplet.
	* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
	* gas/ms1/ms1-16-003.s: Tweak label.
	* gas/ms1/ms1.exp: Adjust target triplet.  Add ms2 test.
	* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
	* gas/ms1/relocs.d: Adjust expected machine name and pcrel
	disassembly.
	* gas/ms1/relocs.exp: Adjust target triplet.

include:
	Add ms2.
	* elf/ms1.h (EF_MS1_CPU_MS2): New.


opcodes:
	Add ms2.
	* ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c,
	ms1-opc.c, ms1-opc.h: Regenerated.

7 files changed, 62 insertions, 8 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 37b9562..d74978e 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,16 @@
+2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Add ms2 support
+	* archures.c (bfd_mach_ms2): Define.
+	* cpu-ms1.c (arch_info_struct): Add ms2 stanza.
+	* elf32-ms1.c (elf32_ms1_machine): Add ms2 case.
+	(ms1_elf_merge_private_bfd_data): Remove unused variables.  Add
+	correct merging logic, with workaround.
+	(ms1_elf_print_private_bfd_data): Add ms2 case.
+	* reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc.
+	* libbfd.h: Regenerated.
+	* bfd-in2.h: Regenerated.
+
 2005-11-07  Steve Ellcey  <sje@cup.hp.com>
 
 	* warning.m4 (AM_BINUTILS_WARNINGS): Default to empty string
diff --git a/bfd/archures.c b/bfd/archures.c
index a96771c..561ddfc 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -320,6 +320,7 @@ DESCRIPTION
 .  bfd_arch_ms1,
 .#define bfd_mach_ms1           1
 .#define bfd_mach_mrisc2        2
+.#define bfd_mach_ms2           3
 .  bfd_arch_pj,
 .  bfd_arch_avr,       {* Atmel AVR microcontrollers.  *}
 .#define bfd_mach_avr1		1
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 7afe437..d857086 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1908,6 +1908,7 @@ enum bfd_architecture
   bfd_arch_ms1,
 #define bfd_mach_ms1           1
 #define bfd_mach_mrisc2        2
+#define bfd_mach_ms2           3
   bfd_arch_pj,
   bfd_arch_avr,       /* Atmel AVR microcontrollers.  */
 #define bfd_mach_avr1          1
@@ -3970,6 +3971,9 @@ This is the 5 bits of a value.  */
 /* Morpho MS1 - Used to tell the linker which vtable entries are used.  */
   BFD_RELOC_MS1_GNU_VTENTRY,
 
+/* Morpho MS1 - 8 bit immediate relocation.  */
+  BFD_RELOC_MS1_PCINSN8,
+
 /* msp430 specific relocation codes  */
   BFD_RELOC_MSP430_10_PCREL,
   BFD_RELOC_MSP430_16_PCREL,
diff --git a/bfd/cpu-ms1.c b/bfd/cpu-ms1.c
index 1a0a726..18d75a0 100644
--- a/bfd/cpu-ms1.c
+++ b/bfd/cpu-ms1.c
@@ -35,8 +35,22 @@ const bfd_arch_info_type arch_info_struct[] =
   FALSE,		        /* The default ?  */
   bfd_default_compatible,	/* Architecture comparison fn.  */
   bfd_default_scan,		/* String to architecture convert fn.  */
+  &arch_info_struct[1]          /* Next in list.  */
+},
+{
+  32,				/* Bits per word - not really true.  */
+  32,				/* Bits per address.  */
+  8,				/* Bits per byte.  */
+  bfd_arch_ms1,			/* Architecture.  */
+  bfd_mach_ms2,		        /* Machine.  */
+  "ms1",			/* Architecture name.  */
+  "ms2",			/* Printable name.  */
+  1,				/* Section align power.  */
+  FALSE,		        /* The default ?  */
+  bfd_default_compatible,	/* Architecture comparison fn.  */
+  bfd_default_scan,		/* String to architecture convert fn.  */
   NULL				/* Next in list.  */
-}
+},
 };
 
 const bfd_arch_info_type bfd_ms1_arch =
diff --git a/bfd/elf32-ms1.c b/bfd/elf32-ms1.c
index 51841e5..c4ce614 100644
--- a/bfd/elf32-ms1.c
+++ b/bfd/elf32-ms1.c
@@ -501,6 +501,7 @@ elf32_ms1_machine (bfd *abfd)
     {
     case EF_MS1_CPU_MRISC:	return bfd_mach_ms1;
     case EF_MS1_CPU_MRISC2:  return bfd_mach_mrisc2;
+    case EF_MS1_CPU_MS2:  return bfd_mach_ms2;
     }
 
   return bfd_mach_ms1;
@@ -548,7 +549,6 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
 {
   flagword     old_flags, new_flags;
   bfd_boolean  error = FALSE;
-  static bfd * last_ibfd = 0;
 
   /* Check if we have the same endianess.  */
   if (_bfd_generic_verify_endian_match (ibfd, obfd) == FALSE)
@@ -569,13 +569,29 @@ ms1_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
 		      ibfd, old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no");
 #endif
 
-  elf_flags_init (obfd) = TRUE;
-
-  if ((new_flags & EF_MS1_CPU_MASK) == EF_MS1_CPU_MRISC2)
+  if (!elf_flags_init (obfd))
+    {
+      old_flags = new_flags;
+      elf_flags_init (obfd) = TRUE;
+    }
+  else if ((new_flags & EF_MS1_CPU_MASK) != (old_flags & EF_MS1_CPU_MASK))
+    {
+      /* CPU has changed.  This is invalid, because MRISC, MRISC2 and
+	 MS2 are not subsets of each other.   */
+      error = 1;
+      
+      /* FIXME:However, until the compiler is multilibbed, preventing
+	 mixing breaks the build.  So we allow merging and use the
+	 greater CPU value.  This is of course unsafe.  */
+      error = 0;
+      if ((new_flags & EF_MS1_CPU_MASK) > (old_flags & EF_MS1_CPU_MASK))
+	old_flags = ((old_flags & ~EF_MS1_CPU_MASK)
+		     | (new_flags & EF_MS1_CPU_MASK));
+    }
+  if (!error)
     {
-      elf_elfheader (obfd)->e_flags = new_flags;
-      last_ibfd = ibfd;
       obfd->arch_info = ibfd->arch_info;
+      elf_elfheader (obfd)->e_flags = old_flags;
     }
 
   return !error;
@@ -598,8 +614,9 @@ ms1_elf_print_private_bfd_data (bfd * abfd, void * ptr)
   switch (flags & EF_MS1_CPU_MASK)
     {
     default:
-    case EF_MS1_CPU_MRISC:	fprintf (file, " ms1-16-002");	break;
+    case EF_MS1_CPU_MRISC:   fprintf (file, " ms1-16-002");	break;
     case EF_MS1_CPU_MRISC2:  fprintf (file, " ms1-16-003");	break;
+    case EF_MS1_CPU_MS2:     fprintf (file, " ms2");	break;
     }
 
   fputc ('\n', file);
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 1fc5416..e05252c 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1764,6 +1764,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_MS1_LO16",
   "BFD_RELOC_MS1_GNU_VTINHERIT",
   "BFD_RELOC_MS1_GNU_VTENTRY",
+  "BFD_RELOC_MS1_PCINSN8",
   "BFD_RELOC_MSP430_10_PCREL",
   "BFD_RELOC_MSP430_16_PCREL",
   "BFD_RELOC_MSP430_16",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index ea73d13..d964f16 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -4424,6 +4424,10 @@ ENUM
   BFD_RELOC_MS1_GNU_VTENTRY
 ENUMDOC
   Morpho MS1 - Used to tell the linker which vtable entries are used.
+ENUM
+  BFD_RELOC_MS1_PCINSN8
+ENUMDOC
+  Morpho MS1 - 8 bit immediate relocation. 
 
 ENUM
   BFD_RELOC_MSP430_10_PCREL