PowerPC VLE

VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE.  For
example
{"evaddw",  VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe.  Also, we don't check
user assembly against the processor type as well as we could.

Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31.  Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.

This patch fixes those problems in the opcode table, and removes
PPCNONE.  I find a plain 0 distracts less from other values.

In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects.  It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.

include/
	* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
	PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
	PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
	PPC_APUINFO_VLE: Define.
opcodes/
	* ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
	cpu for "vle" to e500.
	* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
	(PPCNONE): Delete, substitute throughout.
	(powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
	except for major opcode 4 and 31.
	(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
	* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
	to match other 32-bit archs.
	* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
	(ppc_elf_object_p): Call it.
	(ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
	overlong line.
	(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
	* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
	* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
	_bfd_elf_ppc_at_tprel_transform): Move to..
	* elf-bfd.h: ..here.
	(_bfd_elf_ppc_set_arch): Declare.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
	PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
	PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
	(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
	by vle_opcodes, and that vle flag doesn't enable opcodes.  Don't
	add vle_opcodes twice.
	(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
	* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
	* testsuite/ld-powerpc/apuinfo-vle2.s: New.
	* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.

7 files changed, 128 insertions, 33 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 857caea..fb66662 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,19 @@
+2016-06-07  Alan Modra  <amodra@gmail.com>
+
+	* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
+	to match other 32-bit archs.
+	* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
+	(ppc_elf_object_p): Call it.
+	(ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
+	overlong line.
+	(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
+	* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
+	* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
+	_bfd_elf_ppc_at_tprel_transform): Move to..
+	* elf-bfd.h: ..here.
+	(_bfd_elf_ppc_set_arch): Declare.
+	* bfd-in2.h: Regenerate.
+
 2016-06-06  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr.
diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h
index 196bd70..656d991 100644
--- a/bfd/bfd-in.h
+++ b/bfd/bfd-in.h
@@ -951,13 +951,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
 extern bfd_boolean elf32_tic6x_fix_exidx_coverage
 (struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
 
-/* PowerPC @tls opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tls_transform
-  (unsigned int, unsigned int);
-/* PowerPC @tprel opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tprel_transform
-  (unsigned int, unsigned int);
-
 extern void bfd_elf64_aarch64_init_maps
   (bfd *);
 
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 7292492..b536a59 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -958,13 +958,6 @@ extern bfd_boolean elf32_arm_fix_exidx_coverage
 extern bfd_boolean elf32_tic6x_fix_exidx_coverage
 (struct bfd_section **, unsigned int, struct bfd_link_info *, bfd_boolean);
 
-/* PowerPC @tls opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tls_transform
-  (unsigned int, unsigned int);
-/* PowerPC @tprel opcode transform/validate.  */
-extern unsigned int _bfd_elf_ppc_at_tprel_transform
-  (unsigned int, unsigned int);
-
 extern void bfd_elf64_aarch64_init_maps
   (bfd *);
 
diff --git a/bfd/cpu-powerpc.c b/bfd/cpu-powerpc.c
index 5b77317..fd72cd1 100644
--- a/bfd/cpu-powerpc.c
+++ b/bfd/cpu-powerpc.c
@@ -35,6 +35,10 @@ powerpc_compatible (const bfd_arch_info_type *a,
     default:
       return NULL;
     case bfd_arch_powerpc:
+      if (a->mach == bfd_mach_ppc_vle && b->bits_per_word == 32)
+	return a;
+      if (b->mach == bfd_mach_ppc_vle && a->bits_per_word == 32)
+	return b;
       return bfd_default_compatible (a, b);
     case bfd_arch_rs6000:
       if (b->mach == bfd_mach_rs6k)
diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index 99dbbce..d37c208 100644
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -2368,6 +2368,15 @@ extern bfd_boolean bfd_elf_lookup_section_flags
 extern Elf_Internal_Phdr * _bfd_elf_find_segment_containing_section
   (bfd * abfd, asection * section);
 
+/* PowerPC @tls opcode transform/validate.  */
+extern unsigned int _bfd_elf_ppc_at_tls_transform
+  (unsigned int, unsigned int);
+/* PowerPC @tprel opcode transform/validate.  */
+extern unsigned int _bfd_elf_ppc_at_tprel_transform
+  (unsigned int, unsigned int);
+/* PowerPC elf_object_p tweak.  */
+extern bfd_boolean _bfd_elf_ppc_set_arch (bfd *);
+
 /* Exported interface for writing elf corefile notes. */
 extern char *elfcore_write_note
   (bfd *, char *, int *, const char *, int, const void *, int);
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index accb85f..95ce1dc 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -2196,13 +2196,93 @@ ppc_elf_mkobject (bfd *abfd)
 				  PPC32_ELF_DATA);
 }
 
+/* When defaulting arch/mach, decode apuinfo to find a better match.  */
+
+bfd_boolean
+_bfd_elf_ppc_set_arch (bfd *abfd)
+{
+  unsigned long mach = 0;
+  asection *s;
+  unsigned char *contents;
+
+  if (abfd->arch_info->bits_per_word == 32
+      && bfd_big_endian (abfd))
+    {
+
+      for (s = abfd->sections; s != NULL; s = s->next)
+	if ((elf_section_data (s)->this_hdr.sh_flags & SHF_PPC_VLE) != 0)
+	  break;
+      if (s != NULL)
+	mach = bfd_mach_ppc_vle;
+    }
+
+  if (mach == 0)
+    {
+      s = bfd_get_section_by_name (abfd, APUINFO_SECTION_NAME);
+      if (s != NULL && bfd_malloc_and_get_section (abfd, s, &contents))
+	{
+	  unsigned int apuinfo_size = bfd_get_32 (abfd, contents + 4);
+	  unsigned int i;
+
+	  for (i = 20; i < apuinfo_size + 20 && i + 4 <= s->size; i += 4)
+	    {
+	      unsigned int val = bfd_get_32 (abfd, contents + i);
+	      switch (val >> 16)
+		{
+		case PPC_APUINFO_PMR:
+		case PPC_APUINFO_RFMCI:
+		  if (mach == 0)
+		    mach = bfd_mach_ppc_titan;
+		  break;
+
+		case PPC_APUINFO_ISEL:
+		case PPC_APUINFO_CACHELCK:
+		  if (mach == bfd_mach_ppc_titan)
+		    mach = bfd_mach_ppc_e500mc;
+		  break;
+
+		case PPC_APUINFO_SPE:
+		case PPC_APUINFO_EFS:
+		case PPC_APUINFO_BRLOCK:
+		  if (mach != bfd_mach_ppc_vle)
+		    mach = bfd_mach_ppc_e500;
+
+		case PPC_APUINFO_VLE:
+		  mach = bfd_mach_ppc_vle;
+		  break;
+
+		default:
+		  mach = -1ul;
+		}
+	    }
+	  free (contents);
+	}
+    }
+
+  if (mach != 0 && mach != -1ul)
+    {
+      const bfd_arch_info_type *arch;
+
+      for (arch = abfd->arch_info->next; arch; arch = arch->next)
+	if (arch->mach == mach)
+	  {
+	    abfd->arch_info = arch;
+	    break;
+	  }
+    }
+  return TRUE;
+}
+
 /* Fix bad default arch selected for a 32 bit input bfd when the
-   default is 64 bit.  */
+   default is 64 bit.  Also select arch based on apuinfo.  */
 
 static bfd_boolean
 ppc_elf_object_p (bfd *abfd)
 {
-  if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 64)
+  if (!abfd->arch_info->the_default)
+    return TRUE;
+
+  if (abfd->arch_info->bits_per_word == 64)
     {
       Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
 
@@ -2213,7 +2293,7 @@ ppc_elf_object_p (bfd *abfd)
 	  BFD_ASSERT (abfd->arch_info->bits_per_word == 32);
 	}
     }
-  return TRUE;
+  return _bfd_elf_ppc_set_arch (abfd);
 }
 
 /* Function to set whether a module needs the -mrelocatable bit set.  */
@@ -2519,16 +2599,16 @@ ppc_elf_modify_segment_map (bfd *abfd,
 
 static const struct bfd_elf_special_section ppc_elf_special_sections[] =
 {
-  { STRING_COMMA_LEN (".plt"),             0, SHT_NOBITS,   SHF_ALLOC + SHF_EXECINSTR },
-  { STRING_COMMA_LEN (".sbss"),           -2, SHT_NOBITS,   SHF_ALLOC + SHF_WRITE },
-  { STRING_COMMA_LEN (".sbss2"),          -2, SHT_PROGBITS, SHF_ALLOC },
-  { STRING_COMMA_LEN (".sdata"),          -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
-  { STRING_COMMA_LEN (".sdata2"),         -2, SHT_PROGBITS, SHF_ALLOC },
-  { STRING_COMMA_LEN (".tags"),            0, SHT_ORDERED,  SHF_ALLOC },
-  { STRING_COMMA_LEN (".PPC.EMB.apuinfo"), 0, SHT_NOTE,     0 },
-  { STRING_COMMA_LEN (".PPC.EMB.sbss0"),   0, SHT_PROGBITS, SHF_ALLOC },
-  { STRING_COMMA_LEN (".PPC.EMB.sdata0"),  0, SHT_PROGBITS, SHF_ALLOC },
-  { NULL,                              0,  0, 0,            0 }
+  { STRING_COMMA_LEN (".plt"), 0, SHT_NOBITS, SHF_ALLOC + SHF_EXECINSTR },
+  { STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE },
+  { STRING_COMMA_LEN (".sbss2"), -2, SHT_PROGBITS, SHF_ALLOC },
+  { STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE },
+  { STRING_COMMA_LEN (".sdata2"), -2, SHT_PROGBITS, SHF_ALLOC },
+  { STRING_COMMA_LEN (".tags"), 0, SHT_ORDERED, SHF_ALLOC },
+  { STRING_COMMA_LEN (APUINFO_SECTION_NAME), 0, SHT_NOTE, 0 },
+  { STRING_COMMA_LEN (".PPC.EMB.sbss0"), 0, SHT_PROGBITS, SHF_ALLOC },
+  { STRING_COMMA_LEN (".PPC.EMB.sdata0"), 0, SHT_PROGBITS, SHF_ALLOC },
+  { NULL, 0, 0, 0, 0 }
 };
 
 /* This is what we want for new plt/got.  */
@@ -2637,9 +2717,6 @@ apuinfo_list_finish (void)
   head = NULL;
 }
 
-#define APUINFO_SECTION_NAME	".PPC.EMB.apuinfo"
-#define APUINFO_LABEL		"APUinfo"
-
 /* Scan the input BFDs and create a linked list of
    the APUinfo values that will need to be emitted.  */
 
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 41fe879..70fa5c3 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -2888,12 +2888,15 @@ ppc64_elf_mkobject (bfd *abfd)
 }
 
 /* Fix bad default arch selected for a 64 bit input bfd when the
-   default is 32 bit.  */
+   default is 32 bit.  Also select arch based on apuinfo.  */
 
 static bfd_boolean
 ppc64_elf_object_p (bfd *abfd)
 {
-  if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 32)
+  if (!abfd->arch_info->the_default)
+    return TRUE;
+
+  if (abfd->arch_info->bits_per_word == 32)
     {
       Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
 
@@ -2904,7 +2907,7 @@ ppc64_elf_object_p (bfd *abfd)
 	  BFD_ASSERT (abfd->arch_info->bits_per_word == 64);
 	}
     }
-  return TRUE;
+  return _bfd_elf_ppc_set_arch (abfd);
 }
 
 /* Support for core dump NOTE sections.  */