diff options
author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:06:31 +0800 |
---|---|---|
committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:31:48 +0800 |
commit | 4d8f1ff3bc75dde16f52513de77c7b22a0650f7a (patch) | |
tree | 1e5788add88865a05c582a39e3aa4c28904965ca /bfd | |
parent | 763c4daa35a9f98533d91309917ae70d51893064 (diff) | |
download | gdb-4d8f1ff3bc75dde16f52513de77c7b22a0650f7a.zip gdb-4d8f1ff3bc75dde16f52513de77c7b22a0650f7a.tar.gz gdb-4d8f1ff3bc75dde16f52513de77c7b22a0650f7a.tar.bz2 |
RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds the sub-extension "XTheadZvamo" for the
"XTheadVector" extension, and it provides AMO instructions
for T-Head VECTOR vendor extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support
for "XTheadZvamo" extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi:
* testsuite/gas/riscv/x-thead-vector-zvamo.d: New test.
* testsuite/gas/riscv/x-thead-vector-zvamo.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New.
* opcode/riscv.h (enum riscv_insn_class): Add insn class.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'bfd')
-rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e2c3ffe..97219b6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1374,6 +1374,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2590,6 +2591,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadsync"); case INSN_CLASS_XTHEADVECTOR: return riscv_subset_supports (rps, "xtheadvector"); + case INSN_CLASS_XTHEADZVAMO: + return riscv_subset_supports (rps, "xtheadzvamo"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2836,6 +2839,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadsync"; case INSN_CLASS_XTHEADVECTOR: return "xtheadvector"; + case INSN_CLASS_XTHEADZVAMO: + return "xtheadzvamo"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); |