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| author | Jiawei <jiawei@iscas.ac.cn> | 2023-07-12 20:40:36 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-07-18 11:45:58 +0800 |
| commit | b0a101c53a1caa3f2a9fc2032f703ca4465cfbbb (patch) | |
| tree | 1f982cef3e1a4560c482629eece82363cea2f46f /bfd/elfxx-riscv.c | |
| parent | 7ab8bf1c777644f834ccbc5d1e83d721859ca1ba (diff) | |
| download | gdb-b0a101c53a1caa3f2a9fc2032f703ca4465cfbbb.zip gdb-b0a101c53a1caa3f2a9fc2032f703ca4465cfbbb.tar.gz gdb-b0a101c53a1caa3f2a9fc2032f703ca4465cfbbb.tar.bz2 | |
RISC-V: Supports Zcb extension.
This patch support Zcb extension, contains new compressed instructions,
some instructions depend on other existed extension, like 'zba', 'zbb'
and 'zmmul'. Zcb also imply Zca extension to enable the compressing
features.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcb.d: New test.
* testsuite/gas/riscv/zcb.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_C_LBU): New opcode.
(MASK_C_LBU): New mask.
(MATCH_C_LHU): New opcode.
(MASK_C_LHU): New mask.
(MATCH_C_LH): New opcode.
(MASK_C_LH): New mask.
(MATCH_C_SB): New opcode.
(MASK_C_SB): New mask.
(MATCH_C_SH): New opcode.
(MASK_C_SH): New mask.
(MATCH_C_ZEXT_B): New opcode.
(MASK_C_ZEXT_B): New mask.
(MATCH_C_SEXT_B): New opcode.
(MASK_C_SEXT_B): New mask.
(MATCH_C_ZEXT_H): New opcode.
(MASK_C_ZEXT_H): New mask.
(MATCH_C_SEXT_H): New opcode.
(MASK_C_SEXT_H): New mask.
(MATCH_C_ZEXT_W): New opcode.
(MASK_C_ZEXT_W): New mask.
(MATCH_C_NOT): New opcode.
(MASK_C_NOT): New mask.
(MATCH_C_MUL): New opcode.
(MASK_C_MUL): New mask.
(DECLARE_INSN): New opcode.
* opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func.
(EXTRACT_ZCB_HALFWORD_UIMM): Ditto.
(ENCODE_ZCB_BYTE_UIMM): Ditto.
(ENCODE_ZCB_HALFWORD_UIMM): Ditto.
(VALID_ZCB_BYTE_UIMM): Ditto.
(VALID_ZCB_HALFWORD_UIMM): Ditto.
(enum riscv_insn_class): New extension class.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): New operators.
* riscv-opc.c: New instructions.
Diffstat (limited to 'bfd/elfxx-riscv.c')
| -rw-r--r-- | bfd/elfxx-riscv.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8635187..ee96608 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1173,6 +1173,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvksc", "zvbc", check_implicit_always}, {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, + {"zcb", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1307,6 +1308,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ztso", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {"zca", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} @@ -2494,6 +2496,17 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvksed"); case INSN_CLASS_ZVKSH: return riscv_subset_supports (rps, "zvksh"); + case INSN_CLASS_ZCB: + return riscv_subset_supports (rps, "zcb"); + case INSN_CLASS_ZCB_AND_ZBB: + return (riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zbb")); + case INSN_CLASS_ZCB_AND_ZBA: + return (riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zba")); + case INSN_CLASS_ZCB_AND_ZMMUL: + return (riscv_subset_supports (rps, "zcb") + && riscv_subset_supports (rps, "zmmul")); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2702,6 +2715,14 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvksed"); case INSN_CLASS_ZVKSH: return _("zvksh"); + case INSN_CLASS_ZCB: + return "zcb"; + case INSN_CLASS_ZCB_AND_ZBA: + return _("zcb' and `zba"); + case INSN_CLASS_ZCB_AND_ZBB: + return _("zcb' and `zbb"); + case INSN_CLASS_ZCB_AND_ZMMUL: + return _("zcb' and `zmmul', or `zcb' and `m"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: |