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| author | Mary Bennett <mary.bennett@embecosm.com> | 2023-10-02 03:02:05 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-07 12:06:27 +0800 |
| commit | ccb388ca39f49b611acadce03916837c9c1c1ed1 (patch) | |
| tree | c55e0441952e6b2c821000718ded7b3b3501cf60 /bfd/elfxx-riscv.c | |
| parent | cf0d07fd07117934750e4bb94cfc0349e251afae (diff) | |
| download | gdb-ccb388ca39f49b611acadce03916837c9c1c1ed1.zip gdb-ccb388ca39f49b611acadce03916837c9c1c1ed1.tar.gz gdb-ccb388ca39f49b611acadce03916837c9c1c1ed1.tar.bz2 | |
RISC-V: Add support for XCVmac extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
* testsuite/gas/riscv/cv-mac-insns.d: New test.
* testsuite/gas/riscv/cv-mac-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble information with
the EXTRACT macro implemented.
* riscv-opc.c: Defined the MASK and added
XCVmac instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCVmac.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for uimm.
(enum riscv_insn_class): Added the XCVmac instruction class.
Diffstat (limited to 'bfd/elfxx-riscv.c')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 937ab7a..77789b5 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1359,6 +1359,7 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] = static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = { + {"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2550,6 +2551,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: return riscv_subset_supports (rps, "h"); + case INSN_CLASS_XCVMAC: + return riscv_subset_supports (rps, "xcvmac"); case INSN_CLASS_XTHEADBA: return riscv_subset_supports (rps, "xtheadba"); case INSN_CLASS_XTHEADBB: @@ -2790,6 +2793,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "svinval"; case INSN_CLASS_H: return _("h"); + case INSN_CLASS_XCVMAC: + return "xcvmac"; case INSN_CLASS_XTHEADBA: return "xtheadba"; case INSN_CLASS_XTHEADBB: |