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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-30 22:44:12 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:40 -0600 |
| commit | c62d5acf8478b0cb3c93130cb15fa76aecd93a02 (patch) | |
| tree | c2921c7aa874b3b427e38e487a09fa8a54915e6b /bfd/elfxx-riscv.c | |
| parent | 259a2647dc158e196e4e03719cdc6bb0ff657d1d (diff) | |
| download | gdb-c62d5acf8478b0cb3c93130cb15fa76aecd93a02.zip gdb-c62d5acf8478b0cb3c93130cb15fa76aecd93a02.tar.gz gdb-c62d5acf8478b0cb3c93130cb15fa76aecd93a02.tar.bz2 | |
RISC-V: Add support for the Zvkn ISA extension
Zvkn is part of the vector crypto extensions.
Zvkn is shorthand for the following set of extensions:
- Zvkned
- Zvknhb
- Zvbb
- Zvkt
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvkn extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvkn.d: New test.
* testsuite/gas/riscv/zvkn.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'bfd/elfxx-riscv.c')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 10cdcc2..426139d 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1156,6 +1156,10 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zks", "zbkx", check_implicit_always}, {"zks", "zksed", check_implicit_always}, {"zks", "zksh", check_implicit_always}, + {"zvkn", "zvkned", check_implicit_always}, + {"zvkn", "zvknha", check_implicit_always}, + {"zvkn", "zvknhb", check_implicit_always}, + {"zvkn", "zvbb", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1265,6 +1269,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, |