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authorTsukasa OI <research_trasio@irq.a4lg.com>2023-07-26 01:39:44 +0000
committerTsukasa OI <research_trasio@irq.a4lg.com>2023-07-28 03:39:15 +0000
commit6551c119bf788b6b9e3475e5bacf21d589ba9405 (patch)
treedc548af42fa86cf9908287064183727a02937f90 /bfd/elfxx-riscv.c
parentfdc5ba89ca821fb55726fd6ef2d11e851af463a4 (diff)
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RISC-V: Add actual 'Zvkt' extension support
The 'Zvkt' extension is listed on the added extensions in the GNU Binutils version 2.41 (see binutils/NEWS). However, the support of this extension was actually missing. This commit adds actual support of this extension and adds implications from 'Zvkn' and 'Zvks' superset extensions. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets) Add implications from 'Zvkn' and 'Zvks'. (riscv_supported_std_z_ext): Add 'Zvkt' to the supported extension list.
Diffstat (limited to 'bfd/elfxx-riscv.c')
-rw-r--r--bfd/elfxx-riscv.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b43d2cf..ba51657 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1162,6 +1162,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvkn", "zvknha", check_implicit_always},
{"zvkn", "zvknhb", check_implicit_always},
{"zvkn", "zvbb", check_implicit_always},
+ {"zvkn", "zvkt", check_implicit_always},
{"zvkng", "zvkn", check_implicit_always},
{"zvkng", "zvkg", check_implicit_always},
{"zvknc", "zvkn", check_implicit_always},
@@ -1169,6 +1170,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvks", "zvksed", check_implicit_always},
{"zvks", "zvksh", check_implicit_always},
{"zvks", "zvbb", check_implicit_always},
+ {"zvks", "zvkt", check_implicit_always},
{"zvksg", "zvks", check_implicit_always},
{"zvksg", "zvkg", check_implicit_always},
{"zvksc", "zvks", check_implicit_always},
@@ -1296,6 +1298,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvksc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },