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authorjiawei <jiawei@iscas.ac.cn>2021-11-17 20:10:07 +0800
committerNelson Chu <nelson.chu@sifive.com>2021-11-18 14:43:23 +0800
commitde83e5142d054218f476f7364f795bcaa30efd3f (patch)
treeca33a98af3306f2a3373a7dc238d0247f6e2d703 /bfd/elfxx-riscv.c
parentda05b70e56866fd39288f4ff531ddfa6cb988514 (diff)
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RISC-V: Add instructions and operand set for z[fdq]inx
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to verify if z*inx enabled and use gpr instead of fpr when z*inx is enable. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added support for z*inx extension. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Added register choice for z*inx. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Added disassemble check for z*inx. * riscv-opc.c: Reused INSN_CLASS_* for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'bfd/elfxx-riscv.c')
-rw-r--r--bfd/elfxx-riscv.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index d2ffaa9..91afd4c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2249,6 +2249,15 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_D_AND_C:
return (riscv_subset_supports (rps, "d")
&& riscv_subset_supports (rps, "c"));
+ case INSN_CLASS_F_OR_ZFINX:
+ return (riscv_subset_supports (rps, "f")
+ || riscv_subset_supports (rps, "zfinx"));
+ case INSN_CLASS_D_OR_ZDINX:
+ return (riscv_subset_supports (rps, "d")
+ || riscv_subset_supports (rps, "zdinx"));
+ case INSN_CLASS_Q_OR_ZQINX:
+ return (riscv_subset_supports (rps, "q")
+ || riscv_subset_supports (rps, "zqinx"));
case INSN_CLASS_ZBA:
return riscv_subset_supports (rps, "zba");
case INSN_CLASS_ZBB: