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| author | Renlin Li <renlin.li@arm.com> | 2018-01-18 12:08:40 +0000 |
|---|---|---|
| committer | Renlin Li <renlin.li@arm.com> | 2018-01-24 16:19:47 +0000 |
| commit | 322474019df79a1305e83ff7620a72f31a5c7b55 (patch) | |
| tree | ae7e6030970c16a017c540609ec31f448c6ad32f /bfd/elfnn-aarch64.c | |
| parent | cc40406d1d033abc21de1af5a30f2a5fbb692507 (diff) | |
| download | gdb-322474019df79a1305e83ff7620a72f31a5c7b55.zip gdb-322474019df79a1305e83ff7620a72f31a5c7b55.tar.gz gdb-322474019df79a1305e83ff7620a72f31a5c7b55.tar.bz2 | |
[GAS][AARCH64]Add group relocations to create PC-relative offset.
This is a patch to add the gas support for group relocations to create a
16, 32, 48, or 64 bit PC-relative offset inline.
The following relocations are added along with the test cases:
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
bfd/
2018-01-24 Renlin Li <renlin.li@arm.com>
* reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
gas/
2018-01-24 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reloc_table): add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
(md_apply_fix): Likewise
* testsuite/gas/aarch64/prel_g0.s: New.
* testsuite/gas/aarch64/prel_g0.d: New.
* testsuite/gas/aarch64/prel_g0_nc.s: New.
* testsuite/gas/aarch64/prel_g0_nc.d: New.
* testsuite/gas/aarch64/prel_g1.s: New.
* testsuite/gas/aarch64/prel_g1.d: New.
* testsuite/gas/aarch64/prel_g1_nc.s: New.
* testsuite/gas/aarch64/prel_g1_nc.d: New.
* testsuite/gas/aarch64/prel_g2.s: New.
* testsuite/gas/aarch64/prel_g2.d: New.
* testsuite/gas/aarch64/prel_g2_nc.s: New.
* testsuite/gas/aarch64/prel_g2_nc.d: New.
* testsuite/gas/aarch64/prel_g3.s: New.
* testsuite/gas/aarch64/prel_g3.d: New.
Diffstat (limited to 'bfd/elfnn-aarch64.c')
| -rw-r--r-- | bfd/elfnn-aarch64.c | 108 |
1 files changed, 108 insertions, 0 deletions
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index d5711e0..b84c8ba 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -617,6 +617,114 @@ static reloc_howto_type elfNN_aarch64_howto_table[] = 0xffff, /* dst_mask */ FALSE), /* pcrel_offset */ + /* Group relocations to create a 16, 32, 48 or 64 bit + PC relative address inline. */ + + /* MOV[NZ]: ((S+A-P) >> 0) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G0), /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 17, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G0), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOVK: ((S+A-P) >> 0) & 0xffff [no overflow check] */ + HOWTO64 (AARCH64_R (MOVW_PREL_G0_NC), /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G0_NC), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOV[NZ]: ((S+A-P) >> 16) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G1), /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 17, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G1), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOVK: ((S+A-P) >> 16) & 0xffff [no overflow check] */ + HOWTO64 (AARCH64_R (MOVW_PREL_G1_NC), /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G1_NC), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOV[NZ]: ((S+A-P) >> 32) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G2), /* type */ + 32, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 17, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G2), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOVK: ((S+A-P) >> 32) & 0xffff [no overflow check] */ + HOWTO64 (AARCH64_R (MOVW_PREL_G2_NC), /* type */ + 32, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G2_NC), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* MOV[NZ]: ((S+A-P) >> 48) & 0xffff */ + HOWTO64 (AARCH64_R (MOVW_PREL_G3), /* type */ + 48, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + AARCH64_R_STR (MOVW_PREL_G3), /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + /* Relocations to generate 19, 21 and 33 bit PC-relative load/store addresses: PG(x) is (x & ~0xfff). */ |