PowerPC VLE

VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE.  For
example
{"evaddw",  VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe.  Also, we don't check
user assembly against the processor type as well as we could.

Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31.  Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.

This patch fixes those problems in the opcode table, and removes
PPCNONE.  I find a plain 0 distracts less from other values.

In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects.  It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.

include/
	* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
	PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
	PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
	PPC_APUINFO_VLE: Define.
opcodes/
	* ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
	cpu for "vle" to e500.
	* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
	(PPCNONE): Delete, substitute throughout.
	(powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
	except for major opcode 4 and 31.
	(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
	* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
	to match other 32-bit archs.
	* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
	(ppc_elf_object_p): Call it.
	(ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
	overlong line.
	(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
	* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
	* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
	_bfd_elf_ppc_at_tprel_transform): Move to..
	* elf-bfd.h: ..here.
	(_bfd_elf_ppc_set_arch): Declare.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
	PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
	PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
	(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
	by vle_opcodes, and that vle flag doesn't enable opcodes.  Don't
	add vle_opcodes twice.
	(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
	* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
	* testsuite/ld-powerpc/apuinfo-vle2.s: New.
	* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.

1 files changed, 6 insertions, 3 deletions

diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 41fe879..70fa5c3 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -2888,12 +2888,15 @@ ppc64_elf_mkobject (bfd *abfd)
 }
 
 /* Fix bad default arch selected for a 64 bit input bfd when the
-   default is 32 bit.  */
+   default is 32 bit.  Also select arch based on apuinfo.  */
 
 static bfd_boolean
 ppc64_elf_object_p (bfd *abfd)
 {
-  if (abfd->arch_info->the_default && abfd->arch_info->bits_per_word == 32)
+  if (!abfd->arch_info->the_default)
+    return TRUE;
+
+  if (abfd->arch_info->bits_per_word == 32)
     {
       Elf_Internal_Ehdr *i_ehdr = elf_elfheader (abfd);
 
@@ -2904,7 +2907,7 @@ ppc64_elf_object_p (bfd *abfd)
 	  BFD_ASSERT (abfd->arch_info->bits_per_word == 64);
 	}
     }
-  return TRUE;
+  return _bfd_elf_ppc_set_arch (abfd);
 }
 
 /* Support for core dump NOTE sections.  */