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authorRichard Henderson <rth@redhat.com>2011-06-24 17:38:17 +0000
committerRichard Henderson <rth@redhat.com>2011-06-24 17:38:17 +0000
commit7dbf3b76a24009dfe759b42e5b8544f20c6d9529 (patch)
tree35e6b1238247f6bfcf9fad97be5b6ea8f606d2db /bfd/elf64-alpha.c
parenta60af0db8811f4ea6f5ac98322121ac541eb12e7 (diff)
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PR ld/12928
* elf64-alpha.c (elf64_alpha_relax_tls_get_addr): Recover the tlsgd insn before swapping adjacent insns.
Diffstat (limited to 'bfd/elf64-alpha.c')
-rw-r--r--bfd/elf64-alpha.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c
index 46078ea..6076709 100644
--- a/bfd/elf64-alpha.c
+++ b/bfd/elf64-alpha.c
@@ -3508,6 +3508,13 @@ elf64_alpha_relax_tls_get_addr (struct alpha_relax_info *info, bfd_vma symval,
pos[3] = info->contents + gpdisp->r_offset;
pos[4] = pos[3] + gpdisp->r_addend;
+ /* Beware of the compiler hoisting part of the sequence out a loop
+ and adjusting the destination register for the TLSGD insn. If this
+ happens, there will be a move into $16 before the JSR insn, so only
+ transformations of the first insn pair should use this register. */
+ tlsgd_reg = bfd_get_32 (info->abfd, pos[0]);
+ tlsgd_reg = (tlsgd_reg >> 21) & 31;
+
/* Generally, the positions are not allowed to be out of order, lest the
modified insn sequence have different register lifetimes. We can make
an exception when pos 1 is adjacent to pos 0. */
@@ -3575,13 +3582,6 @@ elf64_alpha_relax_tls_get_addr (struct alpha_relax_info *info, bfd_vma symval,
use_gottprel = FALSE;
new_symndx = is_gd ? ELF64_R_SYM (irel->r_info) : STN_UNDEF;
- /* Beware of the compiler hoisting part of the sequence out a loop
- and adjusting the destination register for the TLSGD insn. If this
- happens, there will be a move into $16 before the JSR insn, so only
- transformations of the first insn pair should use this register. */
- tlsgd_reg = bfd_get_32 (info->abfd, pos[0]);
- tlsgd_reg = (tlsgd_reg >> 21) & 31;
-
switch (!dynamic && !info->link_info->shared)
{
case 1: