diff options
| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
| commit | b930964c425533f2344c6b26d4af17200bb42928 (patch) | |
| tree | 949f69c94cfa475f597e0cd80128fb7fe13f3f6b /bfd/elf32-msp430.c | |
| parent | 21629cf8bc2b16d3c75dff0c3f1222b714bf90c2 (diff) | |
| download | gdb-b930964c425533f2344c6b26d4af17200bb42928.zip gdb-b930964c425533f2344c6b26d4af17200bb42928.tar.gz gdb-b930964c425533f2344c6b26d4af17200bb42928.tar.bz2 | |
MIPS/opcodes: Disassemble the RFE instruction
Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
00: 42000010 c0 0x10
to be produced rather than:
00: 42000010 rfe
even for ISA levels that do include the RFE instruction.
Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a
suitable test case.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".
gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Diffstat (limited to 'bfd/elf32-msp430.c')
0 files changed, 0 insertions, 0 deletions