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| author | Terry Guo <terry.guo@arm.com> | 2014-11-21 11:31:37 +0800 |
|---|---|---|
| committer | Terry Guo <terry.guo@arm.com> | 2014-11-21 11:36:06 +0800 |
| commit | a715796ba188e7ca9eac6e613439b63fe50a677d (patch) | |
| tree | 4dd6a5f47fddcb7f5690e03ee49b51986bc0ffd8 /bfd/elf32-arm.c | |
| parent | 45e44d277a1b558bb77ea0a1962172a06be26594 (diff) | |
| download | gdb-a715796ba188e7ca9eac6e613439b63fe50a677d.zip gdb-a715796ba188e7ca9eac6e613439b63fe50a677d.tar.gz gdb-a715796ba188e7ca9eac6e613439b63fe50a677d.tar.bz2 | |
Support ARM Cortex-M7
include/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* opcode/arm.h (FPU_VFP_EXT_ARMV8xD): New macro.
(FPU_VFP_V5D16): Likewise.
(FPU_VFP_V5_SP_D16): Likewise.
(FPU_ARCH_VFP_V5D16): Likewise.
(FPU_ARCH_VFP_V5_SP_D16): Likewise.
bfd/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Support FPv5.
binutils/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* readelf.c (arm_attr_tag_FP_arch): Extended to support FPv5.
gas/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (fpu_vfp_ext_armv8xd): New.
(arm_cpus): Support cortex-m7.
(arm_fpus): Support fpv5-sp-d16 and fpv5-d16.
(do_vfp_nsyn_cvt_fpv8): Generate error when use D register for S
register only target like FPv5-SP-D16.
(do_neon_cvttb_1): Likewise.
(do_vfp_nsyn_fpv8): Likewise.
(do_vrint_1): Likewise.
(aeabi_set_public_attributes): Set proper FP arch for FPv5.
* doc/c-arm.texi: Document new cpu and fpu names for cortex-m7.
gas/testsuite/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* gas/arm/armv7e-m+fpv5-d16.s: New.
* gas/arm/armv7e-m+fpv5-d16.d: Likewise.
* gas/arm/armv7e-m+fpv5-sp-d16.s: Likewise.
* gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise.
ld/testsuite/ChangeLog:
2014-11-21 Terry Guo <terry.guo@arm.com>
* ld-arm/attr-merge-vfp-4-sp.s: New test source file.
* ld-arm/attr-merge-vfp-5-sp.s: Likewise.
* ld-arm/attr-merge-vfp-5.s: Likewise.
* ld-arm/attr-merge-vfp-8.d: New test.
* ld-arm/attr-merge-vfp-8r.d: Likewise.
* ld-arm/attr-merge-vfp-9.d: Likewise.
* ld-arm/attr-merge-vfp-9r.d: Likewise.
* ld-arm/attr-merge-vfp-10.d: Likewise.
* ld-arm/attr-merge-vfp-10r.d: Likewise.
* ld-arm/attr-merge-vfp-11.d: Likewise.
* ld-arm/attr-merge-vfp-11r.d: Likewise.
* ld-arm/attr-merge-vfp-12.d: Likewise.
* ld-arm/attr-merge-vfp-12r.d: Likewise.
* ld-arm/attr-merge-vfp-13.d: Likewise.
* ld-arm/attr-merge-vfp-13r.d: Likewise.
* ld-arm/attr-merge-vfp-14.d: Likewise.
* ld-arm/attr-merge-vfp-14r.d: Likewise.
* ld-arm/arm-elf.exp: Run the new tests.
Diffstat (limited to 'bfd/elf32-arm.c')
| -rw-r--r-- | bfd/elf32-arm.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index 95f59d5..1ff562c 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -11955,7 +11955,7 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd) when it's 0. It might mean absence of FP hardware if Tag_FP_arch is zero, otherwise it is effectively SP + DP. */ -#define VFP_VERSION_COUNT 8 +#define VFP_VERSION_COUNT 9 static const struct { int ver; @@ -11969,7 +11969,8 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd) {3, 16}, {4, 32}, {4, 16}, - {8, 32} + {8, 32}, + {8, 16} }; int ver; int regs; |