diff options
| author | Kazu Hirata <kazu@codesourcery.com> | 2000-12-03 20:44:04 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@codesourcery.com> | 2000-12-03 20:44:04 +0000 |
| commit | a7c108501aa17c815e4085b2421bca552b292d02 (patch) | |
| tree | 27ed50894040939234ca00b85f11fb6d7afc965f /bfd/elf-m10200.c | |
| parent | bc805888417f16602aeb4bfd3f6e33d32ffcae24 (diff) | |
| download | gdb-a7c108501aa17c815e4085b2421bca552b292d02.zip gdb-a7c108501aa17c815e4085b2421bca552b292d02.tar.gz gdb-a7c108501aa17c815e4085b2421bca552b292d02.tar.bz2 | |
2000-12-03 Kazu Hirata <kazu@hxi.com>
* elf32-arm.h: Fix formatting.
* elf32-avr.c: Likewise.
* elf32-cris.c: Likewise.
* elf32-d10v.c: Likewise.
* elf32-d30v.c: Likewise.
* elf-hppa.h: Likewise.
* elf-m10200.c: Likewise.
* elf-m10300.c: Likewise.
Diffstat (limited to 'bfd/elf-m10200.c')
| -rw-r--r-- | bfd/elf-m10200.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/bfd/elf-m10200.c b/bfd/elf-m10200.c index 1939635..acdb3dd 100644 --- a/bfd/elf-m10200.c +++ b/bfd/elf-m10200.c @@ -505,11 +505,11 @@ mn10200_elf_relocate_section (output_bfd, info, input_bfd, input_section, abs24, imm24, d24 all look the same at the reloc level. It might make the code simpler if we had different relocs for the various relaxable operand types. - + We don't handle imm16->imm8 or d16->d8 as they're very rare and somewhat more difficult to support. */ -static boolean +static boolean mn10200_elf_relax_section (abfd, sec, link_info, again) bfd *abfd; asection *sec; @@ -654,7 +654,6 @@ mn10200_elf_relax_section (abfd, sec, link_info, again) that would be more work, but would require less memory when the linker is run. */ - /* Try to turn a 24bit pc-relative branch/call into a 16bit pc-relative branch/call. */ if (ELF32_R_TYPE (irel->r_info) == (int) R_MN10200_PCREL24) @@ -774,7 +773,6 @@ mn10200_elf_relax_section (abfd, sec, link_info, again) bra lab2 lab1: lab1: - This happens when the bCC can't reach lab2 at assembly time, but due to other relaxations it can reach at link time. */ if (ELF32_R_TYPE (irel->r_info) == (int) R_MN10200_PCREL8) @@ -814,7 +812,7 @@ mn10200_elf_relax_section (abfd, sec, link_info, again) continue; /* Now make sure we are a conditional branch. This may not - be necessary, but why take the chance. + be necessary, but why take the chance. Note these checks assume that R_MN10200_PCREL8 relocs only occur on bCC and bCCx insns. If they occured @@ -904,7 +902,7 @@ mn10200_elf_relax_section (abfd, sec, link_info, again) break; } bfd_put_8 (abfd, code, contents + irel->r_offset - 1); - + /* Set the reloc type and symbol for the first branch from the second branch. */ irel->r_info = nrel->r_info; @@ -929,7 +927,7 @@ mn10200_elf_relax_section (abfd, sec, link_info, again) { bfd_vma value = symval; - /* See if the value will fit in 16 bits. + /* See if the value will fit in 16 bits. We allow any 16bit match here. We prune those we can't handle below. */ if ((long)value < 0x7fff && (long)value > -0x8000) @@ -991,7 +989,7 @@ mn10200_elf_relax_section (abfd, sec, link_info, again) *again = true; break; - /* mov imm24,an -> mov imm16,an + /* mov imm24,an -> mov imm16,an cmp imm24,an -> cmp imm16,an mov (abs24),dn -> mov (abs16),dn mov dn,(abs24) -> mov dn,(abs16) @@ -1053,7 +1051,7 @@ mn10200_elf_relax_section (abfd, sec, link_info, again) add imm24,dn -> add imm16,dn add imm24,an -> add imm16,an sub imm24,dn -> sub imm16,dn - sub imm24,an -> sub imm16,an + sub imm24,an -> sub imm16,an And all d24->d16 in memory ops. */ case 0x78: case 0xd0: @@ -1506,7 +1504,6 @@ mn10200_elf_get_relocated_section_contents (output_bfd, link_info, link_order, return NULL; } - #define TARGET_LITTLE_SYM bfd_elf32_mn10200_vec #define TARGET_LITTLE_NAME "elf32-mn10200" #define ELF_ARCH bfd_arch_mn10200 |