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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-26 12:09:01 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-26 12:11:14 +0000 |
| commit | 239ca5e497dda2c151009d664d500086a5c2173a (patch) | |
| tree | 8ca34ede4d986a81de09cb4e8a77303a3e54b87a /bfd/dwarf2.c | |
| parent | 9ed0136bff648c2f32d7462d3ab9205b61778837 (diff) | |
| download | gdb-239ca5e497dda2c151009d664d500086a5c2173a.zip gdb-239ca5e497dda2c151009d664d500086a5c2173a.tar.gz gdb-239ca5e497dda2c151009d664d500086a5c2173a.tar.bz2 | |
gdb/aarch64: Add named flags for FPCR and FPSR registers
This patch updates FPCR (Floating-point Control Register) and FPSR
(Floating-point Status Register) named fields in AArch64. For detailed
description of named register FPCR and FPSR bit fields see [1] and [2].
Please not that bit fields FIZ, AH and NEP (bits 0, 1 and 2 respectively) in
FPCR are defined starting from Armv8.7 architecture.
[1]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpcr
[2]: https://developer.arm.com/docs/ddi0595/i/aarch64-system-registers/fpsr
Example:
>>> info all-registers fpsr
fpsr 0x10 [ IXC ]
>>> info all-registers fpcr
fpcr 0x0 [ RMode=0 ]
Diffstat (limited to 'bfd/dwarf2.c')
0 files changed, 0 insertions, 0 deletions