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| author | Alan Modra <amodra@gmail.com> | 2020-08-19 08:47:35 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2020-08-19 08:47:35 +0930 |
| commit | 18a8a00ebe3159b65798c6132cb5f93ff4ef6c17 (patch) | |
| tree | d0f2aff39f2687d199bb4f7993995bb3fb0468a5 /bfd/cpu-tilegx.c | |
| parent | d138725a62c3fd04cd1b34352d778d6682c73694 (diff) | |
| download | gdb-18a8a00ebe3159b65798c6132cb5f93ff4ef6c17.zip gdb-18a8a00ebe3159b65798c6132cb5f93ff4ef6c17.tar.gz gdb-18a8a00ebe3159b65798c6132cb5f93ff4ef6c17.tar.bz2 | |
Correct vcmpsq, vcmpuq and xvtlsbb BF field
These shouldn't be optional. The record form of vector instructions
set CR6, giving an expectation that omitting BF should be the same as
specifying CR6.
opcodes/
* ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
vcmpuq and xvtlsbb.
gas/
* testsuite/gas/ppc/int128.s: Correct vcmpuq.
* testsuite/gas/ppc/int128.d: Update.
* testsuite/gas/ppc/xvtlsbb.d: Update.
Diffstat (limited to 'bfd/cpu-tilegx.c')
0 files changed, 0 insertions, 0 deletions