RISC-V: Hypervisor ext: support Privileged Spec 1.12

This is the Hypervisor Extension 1.0

 - Hypervisor Memory-Management Instructions
   HFENCE.VVMA, HFENCE.GVMA,

 - Hypervisor Virtual Machine Load and Store Instructions
   HLV.B, HLV.BU,          HSV.B,
   HLV.H, HLV.HU, HLVX.HU, HSB.H,
   HLV.W, HLV.WU, HLVX.WU, HSV.W,
   HLV.D,                  HSV.D

 - Hypervisor CSRs (some new, some address changed)
   hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
   htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
   vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp,

Note that following were added already as part of svinval extension
support:
   HINVAL.GVMA, HINVAL.VVMA

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>

bfd/
	* cpu-riscv.c (riscv_priv_specs): Added entry for 1.12.
	* cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12.
gas/
	* config/tc-riscv.c (abort_version): Updated comment.
	(validate_riscv_insn): Annotate switch-break.
	* testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor.
	* testsuite/gas/riscv/h-ext-32.s: Likewise.
	* testsuite/gas/riscv/h-ext-64.d: Likewise.
	* testsuite/gas/riscv/h-ext-64.s: Likewise.
include/
	* opcode/riscv-opc.h: Added encodings for hypervisor csrs and
	instrcutions.
opcodes/
	* riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.

1 files changed, 1 insertions, 0 deletions

diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h
index ed5ee7e..b251d63 100644
--- a/bfd/cpu-riscv.h
+++ b/bfd/cpu-riscv.h
@@ -32,6 +32,7 @@ enum riscv_spec_class
   PRIV_SPEC_CLASS_1P9P1,
   PRIV_SPEC_CLASS_1P10,
   PRIV_SPEC_CLASS_1P11,
+  PRIV_SPEC_CLASS_1P12,
   PRIV_SPEC_CLASS_DRAFT,
 };