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authorJan Beulich <jbeulich@novell.com>2005-10-24 07:42:50 +0000
committerJan Beulich <jbeulich@novell.com>2005-10-24 07:42:50 +0000
commit6a2375c6b276cd04a893f7d9a8cd87f3656cad65 (patch)
treed5599e1cbae544c8aa7d68843581c8a63d61b80c /bfd/cpu-ia64-opc.c
parent5e0bd1769ddea4d4b75770e2b9bced019ecbca2d (diff)
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include/opcode/
2005-10-24 Jan Beulich <jbeulich@novell.com> * ia64.h (enum ia64_opnd): Move memory operand out of set of indirect operands. bfd/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of set of indirect operands. gas/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * config/tc-ia64.c (enum reg_symbol): Delete IND_MEM. (dot_rot): Change type of num_* variables. Check for positive count. (ia64_optimize_expr): Re-structure. (md_operand): Check for general register. gas/testsuite/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * gas/ia64/index.[sl]: New. * gas/ia64/rotX.[sl]: New. * gas/ia64/ia64.exp: Run new tests. opcodes/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * ia64-asmtab.c: Regenerate.
Diffstat (limited to 'bfd/cpu-ia64-opc.c')
-rw-r--r--bfd/cpu-ia64-opc.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c
index cbd6a58..360ee9b 100644
--- a/bfd/cpu-ia64-opc.c
+++ b/bfd/cpu-ia64-opc.c
@@ -457,6 +457,10 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
"a general register r0-r3" },
+ /* memory operands: */
+ { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
+ "a memory address" },
+
/* indirect operands: */
{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
"a cpuid register" },
@@ -468,8 +472,6 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
"an itr register" },
{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
"an ibr register" },
- { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
- "an indirect memory address" },
{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
"an msr register" },
{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */