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| author | Tamar Christina <tamar.christina@arm.com> | 2017-12-19 12:05:20 +0000 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-01-15 15:44:11 -0200 |
| commit | 0231dce141801ffcdfef8b7f14cd903a6d3f21ba (patch) | |
| tree | 193eea30265348d6e413321287ad706953bc11a1 /bfd/cpu-cr16.c | |
| parent | 7ebfa8a8441093a287e8896c503a162b673c15f7 (diff) | |
| download | gdb-users/linaro/binutils-2_28-branch.zip gdb-users/linaro/binutils-2_28-branch.tar.gz gdb-users/linaro/binutils-2_28-branch.tar.bz2 | |
Correct disassembly of dot product instructions.users/linaro/binutils-2_28-branch
Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:
v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.
Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.
gas/
PR gas/22559
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.
include/
PR gas/22559
* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.
opcodes/
PR gas/22559
* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
Change-Id: Ie80d878ceaeaca281f85583e77e4e367e2a909ea
Diffstat (limited to 'bfd/cpu-cr16.c')
0 files changed, 0 insertions, 0 deletions