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| author | David S. Miller <davem@redhat.com> | 2012-04-21 19:03:52 +0000 |
|---|---|---|
| committer | David S. Miller <davem@redhat.com> | 2012-04-21 19:03:52 +0000 |
| commit | 8d1b3521dbd074e72764e19fb7c9b430a968e664 (patch) | |
| tree | 7a1c8c8feff2ada052d1a0049e91b612b069264b /bfd/cpu-bfin.c | |
| parent | 4272ccafddc93f492a2c8b3c4a0ffa64a96e94f4 (diff) | |
| download | gdb-8d1b3521dbd074e72764e19fb7c9b430a968e664.zip gdb-8d1b3521dbd074e72764e19fb7c9b430a968e664.tar.gz gdb-8d1b3521dbd074e72764e19fb7c9b430a968e664.tar.bz2 | |
Handle sparc compare-and-branch
SPARC-T4 adds a "compare and branch" instruction which fuses
a compare and a branch instruction into one. The branch
is non-delayed, there are no anulling facilities, and the
displacement is 10-bits.
This also corrects the existing bit test for Branch on
Integer Register. The distinguising characteristic between
Branch on Integer Register and Compare-and-Branch is bit
28. The existing code was checking bit 24 for zero, but
that's pointless because bit 24 is already covered by
the "X_OP2 (insn) == 3" test.
gdb/
* sparc-tdep.c (X_DISP10): Define.
(sparc_analyze_control_transfer): Handle compare-and-branch.
Diffstat (limited to 'bfd/cpu-bfin.c')
0 files changed, 0 insertions, 0 deletions