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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 11:58:47 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-04-15 12:31:45 +0100 |
| commit | 60f993ce170b91876ad41e8f7339c24afd63fac2 (patch) | |
| tree | 2326ba080630de9a1378466903b492084a476616 /bfd/bfd-in2.h | |
| parent | f6b2b12db82f7b76c30ec389a67fbce5d2805323 (diff) | |
| download | gdb-60f993ce170b91876ad41e8f7339c24afd63fac2.zip gdb-60f993ce170b91876ad41e8f7339c24afd63fac2.tar.gz gdb-60f993ce170b91876ad41e8f7339c24afd63fac2.tar.bz2 | |
[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
Diffstat (limited to 'bfd/bfd-in2.h')
| -rw-r--r-- | bfd/bfd-in2.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 4a3fa75..540b9f7 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -3579,6 +3579,9 @@ field in the instruction. */ /* ARM 19-bit pc-relative branch for Branch Future Link instruction. */ BFD_RELOC_ARM_THUMB_BF19, +/* ARM 12-bit pc-relative branch for Low Overhead Loop instructions. */ + BFD_RELOC_ARM_THUMB_LOOP12, + /* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. The lowest bit must be zero and is not stored in the instruction. Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an |