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| author | David Edelsohn <dje.gcc@gmail.com> | 1994-11-30 01:29:26 +0000 |
|---|---|---|
| committer | David Edelsohn <dje.gcc@gmail.com> | 1994-11-30 01:29:26 +0000 |
| commit | 05cedcf6c14a80362a47750f56ad4ebb4d676e11 (patch) | |
| tree | 7a73bbcabcbb89dbe3f0edce2e6fe26fc3cec6bc /bfd/bfd-in2.h | |
| parent | 23c17feaa7b3edfa100ae36e7e883347541ee9d5 (diff) | |
| download | gdb-05cedcf6c14a80362a47750f56ad4ebb4d676e11.zip gdb-05cedcf6c14a80362a47750f56ad4ebb4d676e11.tar.gz gdb-05cedcf6c14a80362a47750f56ad4ebb4d676e11.tar.bz2 | |
Initial ARC support.
Diffstat (limited to 'bfd/bfd-in2.h')
| -rw-r--r-- | bfd/bfd-in2.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index ae32bae..6a25c59 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1028,8 +1028,11 @@ enum bfd_architecture bfd_arch_arm, /* Advanced Risc Machines ARM */ bfd_arch_ns32k, /* National Semiconductors ns32000 */ /* start-sanitize-rce */ - bfd_arch_rce, /* Experimental Motorola RCE */ + bfd_arch_rce, /* Motorola RCE */ /* end-sanitize-rce */ + /* start-sanitize-arc */ + bfd_arch_arc, /* Argonaut RISC Core */ + /* end-sanitize-arc */ bfd_arch_last }; @@ -1510,6 +1513,15 @@ not stored in the instruction. */ BFD_RELOC_ARM_SWI, BFD_RELOC_ARM_MULTI, BFD_RELOC_ARM_CP_OFF_IMM, +/* start-sanitize-arc */ + +/* Argonaut RISC Core (ARC) relocs. +ARC 22 bit pc-relative branch. The lowest two bits must be zero and are +not stored in the instruction. High 20 bits installed in bits 7 through 26 +of instruction. */ + BFD_RELOC_ARC_B22_PCREL, +/* end-sanitize-arc */ + BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; const struct reloc_howto_struct * |