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authorSergey Belyashov <sergey.belyashov@gmail.com>2020-01-02 14:10:40 +0000
committerNick Clifton <nickc@redhat.com>2020-01-02 14:14:59 +0000
commit6655dba246bd164d953fe220a0e3d4eed85bb268 (patch)
tree423258b5dadb447dc649e71c6ce48aaeed8ba385 /bfd/bfd-in2.h
parent0db131fb835e4c4f6a024e86743467e7e01c965e (diff)
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Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well.
PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
Diffstat (limited to 'bfd/bfd-in2.h')
-rw-r--r--bfd/bfd-in2.h28
1 files changed, 25 insertions, 3 deletions
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index ceb53d5..7c13bc8 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1888,9 +1888,13 @@ enum bfd_architecture
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_z80,
-#define bfd_mach_z80strict 1 /* No undocumented opcodes. */
-#define bfd_mach_z80 3 /* With ixl, ixh, iyl, and iyh. */
-#define bfd_mach_z80full 7 /* All undocumented instructions. */
+#define bfd_mach_gbz80 0 /* GameBoy Z80 (reduced instruction set) */
+#define bfd_mach_z80strict 1 /* Z80 without undocumented opcodes. */
+#define bfd_mach_z180 2 /* Z180: successor with additional instructions, but without halves of ix and iy */
+#define bfd_mach_z80 3 /* Z80 with ixl, ixh, iyl, and iyh. */
+#define bfd_mach_ez80_z80 4 /* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
+#define bfd_mach_ez80_adl 5 /* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
+#define bfd_mach_z80full 7 /* Z80 with all undocumented instructions. */
#define bfd_mach_r800 11 /* R800: successor with multiplication. */
bfd_arch_lm32, /* Lattice Mico32. */
#define bfd_mach_lm32 1
@@ -5270,6 +5274,24 @@ BFD_RELOC_XTENSA_ASM_EXPAND. */
/* 8 bit signed offset in (ix+d) or (iy+d). */
BFD_RELOC_Z80_DISP8,
+/* First 8 bits of multibyte (32, 24 or 16 bit) value. */
+ BFD_RELOC_Z80_BYTE0,
+
+/* Second 8 bits of multibyte (32, 24 or 16 bit) value. */
+ BFD_RELOC_Z80_BYTE1,
+
+/* Third 8 bits of multibyte (32 or 24 bit) value. */
+ BFD_RELOC_Z80_BYTE2,
+
+/* Fourth 8 bits of multibyte (32 bit) value. */
+ BFD_RELOC_Z80_BYTE3,
+
+/* Lowest 16 bits of multibyte (32 or 24 bit) value. */
+ BFD_RELOC_Z80_WORD0,
+
+/* Highest 16 bits of multibyte (32 or 24 bit) value. */
+ BFD_RELOC_Z80_WORD1,
+
/* DJNZ offset. */
BFD_RELOC_Z8K_DISP7,