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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2014-05-02 14:12:48 +0100 |
|---|---|---|
| committer | Andrew Bennett <andrew.bennett@imgtec.com> | 2014-05-07 11:47:29 +0100 |
| commit | ae52f4830604b4b82bcbe6ad52208d5efcea2f82 (patch) | |
| tree | 1e0eeeeb414a7fed5c419ade7c289d4ac23b7d4b /bfd/archures.c | |
| parent | f7730599d8876775726866275d5ce392c2669e9e (diff) | |
| download | gdb-ae52f4830604b4b82bcbe6ad52208d5efcea2f82.zip gdb-ae52f4830604b4b82bcbe6ad52208d5efcea2f82.tar.gz gdb-ae52f4830604b4b82bcbe6ad52208d5efcea2f82.tar.bz2 | |
Add MIPS r3 and r5 support.
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5. Secondly it adds support for the eretnc instruction.
ChangeLog:
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
mips32r5 and mips64r5.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (arch_info_struct): Likewise.
* elfxx-mips.c (mips_set_isa_flags): Likewise.
gas/
* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
and mips64r5.
(ISA_HAS_64BIT_FPRS): Likewise.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
(ISA_HAS_DROR): Likewise.
(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
OPTION_MIPS64R5.
(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
(md_parse_option): Likewise.
(s_mipsset): Likewise.
(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
and mips64r5. Also change p5600 entry to be mips32r5.
* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
-mips64r5 command line options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3,
mips32r5, mips64r3 and mips64r5 isas to the testsuite.
* gas/mips/r5.s: New test.
* gas/mips/r5.d: Likewise.
include/opcode/
* mips.h (INSN_ISA_MASK): Updated.
(INSN_ISA32R3): New define.
(INSN_ISA32R5): New define.
(INSN_ISA64R3): New define.
(INSN_ISA64R5): New define.
(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
mips64r5.
(INSN_UPTO32R3): New define.
(INSN_UPTO32R5): New define.
(INSN_UPTO64R3): New define.
(INSN_UPTO64R5): New define.
(ISA_MIPS32R3): New define.
(ISA_MIPS32R5): New define.
(ISA_MIPS64R3): New define.
(ISA_MIPS64R5): New define.
(CPU_MIPS32R3): New define.
(CPU_MIPS32R5): New define.
(CPU_MIPS64R3): New define.
(CPU_MIPS64R5): New define.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
(I34): New define.
(I36): New define.
(I66): New define.
(I68): New define.
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
mips64r5.
(parse_mips_dis_option): Update MSA and virtualization support to
allow mips64r3 and mips64r5.
Diffstat (limited to 'bfd/archures.c')
| -rw-r--r-- | bfd/archures.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/bfd/archures.c b/bfd/archures.c index 4ab5f1d..9b47504 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -182,8 +182,12 @@ DESCRIPTION .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} .#define bfd_mach_mipsisa32 32 .#define bfd_mach_mipsisa32r2 33 +.#define bfd_mach_mipsisa32r3 34 +.#define bfd_mach_mipsisa32r5 36 .#define bfd_mach_mipsisa64 64 .#define bfd_mach_mipsisa64r2 65 +.#define bfd_mach_mipsisa64r3 66 +.#define bfd_mach_mipsisa64r5 68 .#define bfd_mach_mips_micromips 96 . bfd_arch_i386, {* Intel 386 *} .#define bfd_mach_i386_intel_syntax (1 << 0) |