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| author | Simon Marchi <simon.marchi@efficios.com> | 2022-03-16 09:00:27 -0400 |
|---|---|---|
| committer | Simon Marchi <simon.marchi@polymtl.ca> | 2022-03-16 09:00:27 -0400 |
| commit | 978602e83f038106c8254424ca83991d784b37cf (patch) | |
| tree | 2713f291ce01c4b0df77e4cd296ca48c090676f4 /bfd/archures.c | |
| parent | f4f95df31b0172bf182e6a516ba23e299323bb2a (diff) | |
| download | gdb-978602e83f038106c8254424ca83991d784b37cf.zip gdb-978602e83f038106c8254424ca83991d784b37cf.tar.gz gdb-978602e83f038106c8254424ca83991d784b37cf.tar.bz2 | |
bfd: add AMDGCN architecture
Add support for the AMDGCN architecture to BFD.
This is the bare minimum to get
$ ./configure --target=amdgcn-hsa-amdhsa --disable-gas
$ make all-binutils
working later in this series.
The specific AMDGCN models added here are a bit arbitrary, based on
what we intend to initially support in GDB. This list will need to be
updated in the future anyway. The complete up-to-date list of existing
AMDGPU models can be found here:
https://llvm.org/docs/AMDGPUUsage.html#processors
The ELF format for this architecture is documented here:
https://llvm.org/docs/AMDGPUUsage.html#elf-code-object
The flags for the "HSA" OS ABI are properly versioned and documented on
that page. But the NONE, PAL and MESA3D OS ABIs are not well documented
nor versioned. Taking a peek at the LLVM source code, we see that they
encode their flags the same way as HSA v3. For example, for PAL:
https://github.com/llvm/llvm-project/blob/c8b614cd74a92d85936aed5ac7c642af75ffdc29/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp#L601
So at least, we know that all AMDGPU objects (of which AMDGCN objects
are a subset of) at the time of writing encode the specific GPU model in
the EF_AMDGPU_MACH field of e_flags.
bfd/ChangeLog:
* Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES):
Add cpu-amdgcn.c.
(BFD64_BACKENDS): Add elf64-amdgcn.lo.
(BFD64_BACKENDS_CFILES): Add elf64-amdgcn.c.
* Makefile.in: Re-generate.
* cpu-amdgcn.c: New.
* elf64-amdgcn.c: New.
* archures.c (bfd_architecture): Add bfd_arch_amdgcn and related
mach defines.
(bfd_amdgcn_arch): New.
(bfd_archures_list): Add bfd_amdgcn_arch.
* bfd-in2.h: Re-generate.
* config.bfd: Handle amdgcn* target.
* configure.ac: Handle amdgcn_elf64_le_vec.
* configure: Re-generate.
* elf-bfd.h (elf_target_id): Add AMDGCN_ELF_DATA.
* targets.c (amdgcn_elf64_le_vec): New.
(_bfd_target_vector): Add amdgcn_elf64_le_vec.
include/ChangeLog:
* elf/amdgpu.h: New.
* elf/common.h (ELFOSABI_AMDGPU_HSA): Add.
Change-Id: I969f7b14960797e88891c308749a6e341eece5b2
Diffstat (limited to 'bfd/archures.c')
| -rw-r--r-- | bfd/archures.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/bfd/archures.c b/bfd/archures.c index d19b5d7..fac9fe8 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -559,6 +559,19 @@ DESCRIPTION . bfd_arch_loongarch, {* LoongArch *} .#define bfd_mach_loongarch32 1 .#define bfd_mach_loongarch64 2 +. bfd_arch_amdgcn, {* AMDGCN *} +.#define bfd_mach_amdgcn_unknown 0x000 +.#define bfd_mach_amdgcn_gfx900 0x02c +.#define bfd_mach_amdgcn_gfx904 0x02e +.#define bfd_mach_amdgcn_gfx906 0x02f +.#define bfd_mach_amdgcn_gfx908 0x030 +.#define bfd_mach_amdgcn_gfx90a 0x03f +.#define bfd_mach_amdgcn_gfx1010 0x033 +.#define bfd_mach_amdgcn_gfx1011 0x034 +.#define bfd_mach_amdgcn_gfx1012 0x035 +.#define bfd_mach_amdgcn_gfx1030 0x036 +.#define bfd_mach_amdgcn_gfx1031 0x037 +.#define bfd_mach_amdgcn_gfx1032 0x038 . bfd_arch_last . }; */ @@ -614,6 +627,7 @@ DESCRIPTION extern const bfd_arch_info_type bfd_aarch64_arch; extern const bfd_arch_info_type bfd_alpha_arch; +extern const bfd_arch_info_type bfd_amdgcn_arch; extern const bfd_arch_info_type bfd_arc_arch; extern const bfd_arch_info_type bfd_arm_arch; extern const bfd_arch_info_type bfd_avr_arch; @@ -704,6 +718,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = #else &bfd_aarch64_arch, &bfd_alpha_arch, + &bfd_amdgcn_arch, &bfd_arc_arch, &bfd_arm_arch, &bfd_avr_arch, |