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authorEric B. Weddington <eric.weddington@atmel.com>2011-03-22 18:10:48 +0000
committerEric B. Weddington <eric.weddington@atmel.com>2011-03-22 18:10:48 +0000
commit8cc66334fa03f92b70da1a17685a093b6b0850ba (patch)
tree3c347ee26f7d734336dbf0c44bbffdc0af9ccd7a /bfd/archures.c
parent3167638f1e8e74e15650adda08449c2e32572552 (diff)
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/bfd:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * archures.c: Add AVR XMEGA architecture information. * cpu-avr.c (arch_info_struct): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. (elf32_avr_object_p): Likewise. /gas: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (struct avr_opcodes_s): Add opcode field. (AVR_INSN): Change definition to match. (avr_opcodes): Likewise, change to match. (mcu_types): Add XMEGA architecture names and new XMEGA device names. (md_show_usage): Add XMEGA architecture names. (avr_operand): Add 'E' constraint for DES instruction of XMEGA devices. Add support for SPM Z+ instruction. * doc/c-avr.texi: Add documentation for XMEGA architectures and devices. /include/opcode: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): New instruction set flags. (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. /ld: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures. (eavrxmega?.c): Likewise. * configure.tgt (targ_extra_emuls): Likewise. * emulparams/avrxmega1.sh: New file. * emulparams/avrxmega2.sh: Likewise. * emulparams/avrxmega3.sh: Likewise. * emulparams/avrxmega4.sh: Likewise. * emulparams/avrxmega5.sh: Likewise. * emulparams/avrxmega6.sh: Likewise. * emulparams/avrxmega7.sh: Likewise. * emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation): Add avrxmega6, avrxmega7 to list of architectures for no stubs. /opcodes: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr-dis.c (avr_operand): Add opcode_str parameter. Check for post-increment to support LPM Z+ instruction. Add support for 'E' constraint for DES instruction. (print_insn_avr): Adjust calls to avr_operand. Rename variable.
Diffstat (limited to 'bfd/archures.c')
-rw-r--r--bfd/archures.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/bfd/archures.c b/bfd/archures.c
index 0efc658..cd8500f 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -376,6 +376,13 @@ DESCRIPTION
.#define bfd_mach_avr5 5
.#define bfd_mach_avr51 51
.#define bfd_mach_avr6 6
+.#define bfd_mach_avrxmega1 101
+.#define bfd_mach_avrxmega2 102
+.#define bfd_mach_avrxmega3 103
+.#define bfd_mach_avrxmega4 104
+.#define bfd_mach_avrxmega5 105
+.#define bfd_mach_avrxmega6 106
+.#define bfd_mach_avrxmega7 107
. bfd_arch_bfin, {* ADI Blackfin *}
.#define bfd_mach_bfin 1
. bfd_arch_cr16, {* National Semiconductor CompactRISC (ie CR16). *}