Add support for RISC-V architecture.

bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.

1 files changed, 28 insertions, 4 deletions

diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 64658c5..661155c 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -481,6 +481,7 @@ ALL_MACHINES = \
 	cpu-plugin.lo \
 	cpu-powerpc.lo \
 	cpu-rs6000.lo \
+	cpu-riscv.lo \
 	cpu-rl78.lo \
 	cpu-rx.lo \
 	cpu-s390.lo \
@@ -568,6 +569,7 @@ ALL_MACHINES_CFILES = \
 	cpu-plugin.c \
 	cpu-powerpc.c \
 	cpu-rs6000.c \
+	cpu-riscv.c \
 	cpu-rl78.c \
 	cpu-rx.c \
 	cpu-s390.c \
@@ -1006,18 +1008,21 @@ BFD64_BACKENDS = \
 	elf64-hppa.lo \
 	elf64-ia64.lo \
 	elf64-ia64-vms.lo \
+	elfxx-ia64.lo \
+	elfn32-mips.lo \
 	elf64-mips.lo \
+	elfxx-mips.lo \
 	elf64-mmix.lo \
 	elf64-ppc.lo \
+	elf32-riscv.lo \
+	elf64-riscv.lo \
+	elfxx-riscv.lo \
 	elf64-s390.lo \
 	elf64-sh64.lo \
 	elf64-sparc.lo \
 	elf64-tilegx.lo \
 	elf64-x86-64.lo \
 	elf64.lo \
-	elfn32-mips.lo \
-	elfxx-ia64.lo \
-	elfxx-mips.lo \
 	mach-o-aarch64.lo \
 	mach-o-x86-64.lo \
 	mmo.lo \
@@ -1057,6 +1062,7 @@ BFD64_BACKENDS_CFILES = \
 	elfxx-aarch64.c \
 	elfxx-ia64.c \
 	elfxx-mips.c \
+	elfxx-riscv.c \
 	mach-o-aarch64.c \
 	mach-o-x86-64.c \
 	mmo.c \
@@ -1122,7 +1128,9 @@ SOURCE_CFILES = \
 
 BUILD_CFILES = \
 	elf32-aarch64.c elf64-aarch64.c \
-	elf32-ia64.c elf64-ia64.c peigen.c pepigen.c pex64igen.c
+	elf32-ia64.c elf64-ia64.c \
+	elf32-riscv.c elf64-riscv.c \
+	peigen.c pepigen.c pex64igen.c
 
 CFILES = $(SOURCE_CFILES) $(BUILD_CFILES)
 SOURCE_HFILES = \
@@ -1412,6 +1420,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pj.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-powerpc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-riscv.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rl78.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rs6000.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rx.Plo@am__quote@
@@ -1501,6 +1510,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or1k.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-riscv.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rl78.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rx.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s390.Plo@am__quote@
@@ -1532,6 +1542,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sh64.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@
@@ -1543,6 +1554,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-aarch64.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-ia64.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-mips.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-riscv.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-sparc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-tilegx.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epoc-pe-arm.Plo@am__quote@
@@ -2080,6 +2092,18 @@ elf64-ia64.c : elfnn-ia64.c
 	$(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new
 	mv -f elf64-ia64.new elf64-ia64.c
 
+elf32-riscv.c : elfnn-riscv.c
+	rm -f elf32-riscv.c
+	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new
+	sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new
+	mv -f elf32-riscv.new elf32-riscv.c
+
+elf64-riscv.c : elfnn-riscv.c
+	rm -f elf64-riscv.c
+	echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new
+	sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new
+	mv -f elf64-riscv.new elf64-riscv.c
+
 peigen.c : peXXigen.c
 	rm -f peigen.c
 	$(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new