Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.

	* opcode/s12z.h: Undef REG_Y.

2 files changed, 18 insertions, 10 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index c78b42b..bc66851 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-01-02  Christian Biesinger  <cbiesinger@google.com>
+
+	* opcode/s12z.h: Undef REG_Y.
+
 2020-01-01  Alan Modra  <amodra@gmail.com>
 
 	Update year range in copyright notice of all files.
diff --git a/include/opcode/s12z.h b/include/opcode/s12z.h
index 7e38ac5..3fd2dd0 100644
--- a/include/opcode/s12z.h
+++ b/include/opcode/s12z.h
@@ -2,25 +2,30 @@
 #define S12Z_H
 
 /* This byte is used to prefix instructions in "page 2" of the opcode
-   space */
+   space.  */
 #define PAGE2_PREBYTE (0x1b)
 
 struct reg
 {
-  char      *name;   /* The canonical name of the register */
-  int       bytes;   /* its size, in bytes */
+  char      *name;   /* The canonical name of the register.  */
+  int       bytes;   /* its size, in bytes.  */
 };
 
 
 /* How many registers do we have.  Actually there are only 13,
    because CCL and CCH are the low and high bytes of CCW.  But
    for assemnbly / disassembly purposes they are considered
-   distinct registers. */
+   distinct registers.  */
 #define S12Z_N_REGISTERS 15
 
 extern const struct reg registers[S12Z_N_REGISTERS];
 
-enum {
+/* Solaris defines REG_Y in sys/regset.h; undef it here to avoid
+   breaking compilation when this target is enabled.  */
+#undef REG_Y
+
+enum
+  {
     REG_D2 = 0,
     REG_D3,
     REG_D4,
@@ -38,7 +43,7 @@ enum {
     REG_CCW
   };
 
-/* Any of the registers d0, d1, ... d7 */
+/* Any of the registers d0, d1, ... d7.  */
 #define REG_BIT_Dn \
 ((0x1U << REG_D2) | \
  (0x1U << REG_D3) | \
@@ -49,23 +54,22 @@ enum {
  (0x1U << REG_D0) | \
  (0x1U << REG_D1))
 
-/* Any of the registers x, y or z */
+/* Any of the registers x, y or z.  */
 #define REG_BIT_XYS \
 ((0x1U << REG_X) | \
  (0x1U << REG_Y) | \
  (0x1U << REG_S))
 
-/* Any of the registers x, y, z or p */
+/* Any of the registers x, y, z or p.  */
 #define REG_BIT_XYSP \
 ((0x1U << REG_X)  | \
  (0x1U << REG_Y)  | \
  (0x1U << REG_S)  | \
  (0x1U << REG_P))
 
-/* The x register or the y register */
+/* The x register or the y register.  */
 #define REG_BIT_XY \
 ((0x1U << REG_X) | \
  (0x1U << REG_Y))
 
-
 #endif