gas/testsuite/

	* gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d,
	gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions
	and expanded PC-relative offsets.

	opcodes/
	* arm-dis.c (coprocessor_opcodes): Use %A instead of %C.  Remove
	generic coprocessor instructions for FPA loads and stores.
	(print_insn_coprocessor): Remove %C support.  Display address for
	PC-relative offsets in %A.

7 files changed, 48 insertions, 50 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index ea1fd51..4b89cf0 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2009-11-12  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d,
+	gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions
+	and expanded PC-relative offsets.
+
 2009-11-11  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/prefix.d: Swap order of ADDR and REP prefixes.
diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d
index 86340c4..e041270 100644
--- a/gas/testsuite/gas/arm/copro.d
+++ b/gas/testsuite/gas/arm/copro.d
@@ -13,12 +13,12 @@ Disassembly of section .text:
 0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
 0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!.*
 0+014 <[^>]*> 5cf31710 	ldclpl	7, cr1, \[r3\], #64.*
-0+018 <[^>]*> ed1f8001 	ldc	0, cr8, \[pc, #-4\]
+0+018 <[^>]*> ed1f8001 	ldc	0, cr8, \[pc, #-4\]	; .* <foo>
 0+01c <[^>]*> ed830500 	cfstr32	mvfx0, \[r3\]
 0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
 0+024 <[^>]*> 0da2c419 	cfstrseq	mvf12, \[r2, #100\]!.*
 0+028 <[^>]*> 3ca4860c 	stccc	6, cr8, \[r4\], #48.*
-0+02c <[^>]*> ed0f7101 	stfs	f7, \[pc, #-4\]
+0+02c <[^>]*> ed0f7101 	stfs	f7, \[pc, #-4\]	; .* <bar>
 0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
 0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, pc, cr1, cr2, \{7\}
 0+038 <[^>]*> ee215711 	mcr	7, 1, r5, cr1, cr1, \{0\}
diff --git a/gas/testsuite/gas/arm/float.d b/gas/testsuite/gas/arm/float.d
index 16d7eba..c049430 100644
--- a/gas/testsuite/gas/arm/float.d
+++ b/gas/testsuite/gas/arm/float.d
@@ -119,13 +119,13 @@ Disassembly of section .text:
 0+1bc <[^>]+> 0ef3f114 ?	cnfeeq	f3, f4
 0+1c0 <[^>]+> 0ef4f117 ?	cnfeeq	f4, f7
 0+1c4 <[^>]+> eef4f11d ?	cnfe	f4, #5\.0
-0+1c8 <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]	; \(ldc 2, cr0, \[r0\]\)
-0+1cc <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]	; \(ldc 2, cr0, \[r0\]\)
+0+1c8 <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]
+0+1cc <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]
 0+1d0 <[^>]+> ed911210 ?	lfm	f1, 4, \[r1, #64\].*
 0+1d4 <[^>]+> edae22ff ?	sfm	f2, 4, \[lr, #1020\]!.*
 0+1d8 <[^>]+> 0c68f2ff ?	sfmeq	f7, 3, \[r8\], #-1020.*
-0+1dc <[^>]+> eddf6200 ?	lfm	f6, 2, \[pc\]	; \(ldcl 2, cr6, \[pc\]\)
-0+1e0 <[^>]+> eca8f203 ?	sfm	f7, 1, \[r8\], #12	; \(stc 2, cr15, \[r8\], #12\)
+0+1dc <[^>]+> eddf6200 ?	lfm	f6, 2, \[pc\]	; .* <l\+.*>
+0+1e0 <[^>]+> eca8f203 ?	sfm	f7, 1, \[r8\], #12
 0+1e4 <[^>]+> 0d16520c ?	lfmeq	f5, 4, \[r6, #-48\].*
 0+1e8 <[^>]+> 1d42c209 ?	sfmne	f4, 3, \[r2, #-36\].*
 0+1ec <[^>]+> 1d62c209 ?	sfmne	f4, 3, \[r2, #-36\]!.*
diff --git a/gas/testsuite/gas/arm/fp-save.d b/gas/testsuite/gas/arm/fp-save.d
index ddf1beb..d32d930 100644
--- a/gas/testsuite/gas/arm/fp-save.d
+++ b/gas/testsuite/gas/arm/fp-save.d
@@ -6,4 +6,4 @@
 .*: *file format .*arm.*
 
 Disassembly of section .text:
-0+00 <[^>]*> ed2dc203[ 	]+sfm[ 	]+f4, 1, \[sp, #-12\]!	; \(stc 2, cr12, \[sp, #-12\]!\)
+0+00 <[^>]*> ed2dc203[ 	]+sfm[ 	]+f4, 1, \[sp, #-12\]!
diff --git a/gas/testsuite/gas/arm/fpa-mem.d b/gas/testsuite/gas/arm/fpa-mem.d
index 18000b9..4a638e1 100644
--- a/gas/testsuite/gas/arm/fpa-mem.d
+++ b/gas/testsuite/gas/arm/fpa-mem.d
@@ -24,11 +24,11 @@ Disassembly of section .text:
 0+34 <[^>]*> ec600101 ?	stfe	f0, \[r0\], #-4
 0+38 <[^>]*> edc08100 ?	stfp	f0, \[r0\]
 0+3c <[^>]*> ec608101 ?	stfp	f0, \[r0\], #-4
-0+40 <[^>]*> ed900200 ?	lfm	f0, 4, \[r0\]	; \(ldc 2, cr0, \[r0\]\)
-0+44 <[^>]*> ed900200 ?	lfm	f0, 4, \[r0\]	; \(ldc 2, cr0, \[r0\]\)
+0+40 <[^>]*> ed900200 ?	lfm	f0, 4, \[r0\]
+0+44 <[^>]*> ed900200 ?	lfm	f0, 4, \[r0\]
 0+48 <[^>]*> ed10020c ?	lfm	f0, 4, \[r0, #-48\].*
-0+4c <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]	; \(stc 2, cr0, \[r0\]\)
+0+4c <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]
 0+50 <[^>]*> ed00020c ?	sfm	f0, 4, \[r0, #-48\].*
-0+54 <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]	; \(stc 2, cr0, \[r0\]\)
+0+54 <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]
 0+58 <[^>]*> 5d800100 ?	stfpls	f0, \[r0\]
 0+5c <[^>]*> 5d800100 ?	stfpls	f0, \[r0\]
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 90d297c..b346c81 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2009-11-12  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* arm-dis.c (coprocessor_opcodes): Use %A instead of %C.  Remove
+	generic coprocessor instructions for FPA loads and stores.
+	(print_insn_coprocessor): Remove %C support.  Display address for
+	PC-relative offsets in %A.
+
 2009-11-11  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (all_prefixes): New.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 28e503e..0d99c6c 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -69,7 +69,6 @@ struct opcode16
    %u			print condition code (unconditional in ARM mode)
    %A			print address for ldc/stc/ldf/stf instruction
    %B			print vstm/vldm register list
-   %C			print vstr/vldr address operand
    %I                   print cirrus signed shift immediate: bits 0..3|4..6
    %F			print the COUNT field of a LFM/SFM instruction.
    %P			print floating point precision in arithmetic insn
@@ -248,8 +247,8 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
   {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
   {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
-  {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A\t; (stc%22'l%c %8-11d, cr%12-15d, %A)"},
-  {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A\t; (ldc%22'l%c %8-11d, cr%12-15d, %A)"},
+  {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
+  {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 
   /* Register load/store.  */
   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
@@ -258,8 +257,8 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
   {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
-  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
-  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
+  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
+  {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
   {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
   {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
   {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
@@ -1808,19 +1807,26 @@ print_insn_coprocessor (bfd_vma pc,
 
 		case 'A':
 		  {
-		    int offset = given & 0xff;
+		    int rn = (given >> 16) & 0xf;
+  		    int offset = given & 0xff;
 
 		    func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
 
-		    value_in_comment = offset * 4;
-		    if (NEGATIVE_BIT_SET)
-		      value_in_comment = - value_in_comment;
-		    
+		    if (PRE_BIT_SET || WRITEBACK_BIT_SET)
+		      {
+			/* Not unindexed.  The offset is scaled.  */
+			offset = offset * 4;
+			if (NEGATIVE_BIT_SET)
+			  offset = - offset;
+			if (rn != 15)
+			  value_in_comment = offset;
+		      }
+
 		    if (PRE_BIT_SET)
 		      {
 			if (offset)
 			  func (stream, ", #%d]%s",
-				value_in_comment,
+				offset,
 				WRITEBACK_BIT_SET ? "!" : "");
 			else
 			  func (stream, "]");
@@ -1832,7 +1838,7 @@ print_insn_coprocessor (bfd_vma pc,
 			if (WRITEBACK_BIT_SET)
 			  {
 			    if (offset)
-			      func (stream, ", #%d", value_in_comment);
+			      func (stream, ", #%d", offset);
 			  }
 			else
 			  {
@@ -1840,6 +1846,12 @@ print_insn_coprocessor (bfd_vma pc,
 			    value_in_comment = offset;
 			  }
 		      }
+		    if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
+		      {
+			func (stream, "\t; ");
+			info->print_address_func (offset + pc
+						  + info->bytes_per_chunk * 2, info);
+		      }
 		  }
 		  break;
 
@@ -1857,33 +1869,6 @@ print_insn_coprocessor (bfd_vma pc,
 		  }
 		  break;
 
-		case 'C':
-		  {
-		    int rn = (given >> 16) & 0xf;
-		    int offset = (given & 0xff) * 4;
-
-		    func (stream, "[%s", arm_regnames[rn]);
-
-		    if (offset)
-		      {
-			if (NEGATIVE_BIT_SET)
-			  offset = - offset;
-			func (stream, ", #%d", offset);
-			if (rn != 15)
-			  value_in_comment = offset;
-		      }
-		    func (stream, "]");
-		    if (rn == 15)
-		      {
-			func (stream, "\t; ");
-			/* FIXME: Unsure if info->bytes_per_chunk is the
-			   right thing to use here.  */
-			info->print_address_func (offset + pc
-						  + info->bytes_per_chunk * 2, info);
-		      }
-		  }
-		  break;
-
 		case 'c':
 		  func (stream, "%s", arm_conditional[cond]);
 		  break;