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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2020-06-16 17:00:33 +0100 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2020-06-25 18:07:33 +0100 |
| commit | 6d74da72dacdbbe2b87a6b931e0f7edc3d3463e3 (patch) | |
| tree | 5d43d213221a997b1ed1c8f30efd25373d9b3315 | |
| parent | 2e52d038246520ee8f8d8344da18303154a421a6 (diff) | |
| download | gdb-6d74da72dacdbbe2b87a6b931e0f7edc3d3463e3.zip gdb-6d74da72dacdbbe2b87a6b931e0f7edc3d3463e3.tar.gz gdb-6d74da72dacdbbe2b87a6b931e0f7edc3d3463e3.tar.bz2 | |
gdb/riscv: Loop over all registers for 'info all-registers'
Currently the 'info all-registers' command only loops over those
registers that are known to GDB. Any registers that are unknown, that
is, are mentioned in the target description, but are not something GDB
otherwise knows, will not be displayed.
This feels wrong, so this commit fixes this mistake. The output of
'info all-registers' now matches 'info registers all'.
gdb/ChangeLog:
* riscv-tdep.c (riscv_print_registers_info): Loop over all
registers, not just the known core set of registers.
gdb/testsuite/ChangeLog:
* gdb.arch/riscv-tdesc-regs.exp: New test cases.
| -rw-r--r-- | gdb/ChangeLog | 5 | ||||
| -rw-r--r-- | gdb/riscv-tdep.c | 2 | ||||
| -rw-r--r-- | gdb/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp | 10 |
4 files changed, 17 insertions, 4 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index f3ede94..0a36c6b 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,5 +1,10 @@ 2020-06-25 Andrew Burgess <andrew.burgess@embecosm.com> + * riscv-tdep.c (riscv_print_registers_info): Loop over all + registers, not just the known core set of registers. + +2020-06-25 Andrew Burgess <andrew.burgess@embecosm.com> + * riscv-tdep.c (riscv_register_name): Return NULL for duplicate fflags, frm, and fcsr registers. (riscv_register_reggroup_p): Remove unknown CSRs from save and diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index cfc45d1..b86ba63 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -1071,7 +1071,7 @@ riscv_print_registers_info (struct gdbarch *gdbarch, else reggroup = general_reggroup; - for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum) + for (regnum = 0; regnum < gdbarch_num_cooked_regs (gdbarch); ++regnum) { /* Zero never changes, so might as well hide by default. */ if (regnum == RISCV_ZERO_REGNUM && !print_all) diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index 0090327..8ad2448 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2020-06-25 Andrew Burgess <andrew.burgess@embecosm.com> + * gdb.arch/riscv-tdesc-regs.exp: New test cases. + +2020-06-25 Andrew Burgess <andrew.burgess@embecosm.com> + * gdb.arch/riscv-tdesc-regs.exp: Extend test case. 2020-06-25 Andrew Burgess <andrew.burgess@embecosm.com> diff --git a/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp b/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp index 9feddba..1be32e0 100644 --- a/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp +++ b/gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp @@ -80,11 +80,15 @@ gdb_test "info registers \$csr0" "Invalid register `csr0'" gdb_test "info registers \$dscratch0" "dscratch0\[ \t\]+.*" gdb_test "info registers \$dscratch" "dscratch\[ \t\]+.*" -foreach rgroup {all save restore} { +foreach rgroup {x_all all save restore} { # Now use 'info registers all' to see how many times the floating # point status registers show up in the output. array set reg_counts {} - set test "info registers $rgroup" + if {$rgroup == "x_all"} { + set test "info all-registers" + } else { + set test "info registers $rgroup" + } gdb_test_multiple $test $test { -re ".*info registers all\r\n" { verbose -log "Skip to first register" @@ -107,7 +111,7 @@ foreach rgroup {all save restore} { set count 0 } if {($reg == "unknown_csr" || $reg == "dscratch") \ - && $rgroup != "all"} { + && $rgroup != "all" && $rgroup != "x_all"} { gdb_assert {$count == 0} \ "register $reg not seen in reggroup $rgroup" } else { |