aarch64: Extract Condition flag manipulation feature from Armv8.4-A

Extract FLAGM (Condition flag manipulation) feature from Armv8.4-A.
Please note that FLAGM stays a Armv8.4-A feature but now can be
assigned to other architectures or CPUs.

New -march option +flagm is added to enable independently this
feature.

10 files changed, 76 insertions, 6 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3693776..c289dd7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
 2020-11-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
+	* NEWS: Update news.
+	* config/tc-aarch64.c: New feature flag +flagm.
+	* doc/c-aarch64.texi: Update docs.
+	* testsuite/gas/aarch64/flagm.d: New test.
+	* testsuite/gas/aarch64/flagm.s: New test.
+
+2020-11-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
 	* config/tc-arm.c (arm_cpus): Add Cortex-A78C.
 	* doc/c-arm.texi: Document -mcpu=cortex-a78c.
 	* testsuite/gas/arm/cpu-cortex-a78c.d: New test.
diff --git a/gas/NEWS b/gas/NEWS
index 8841507..1d4b4be 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -25,7 +25,9 @@
   AArch64.
 
 * Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE
-  feature.
+  feature in AArch64.
+
+* Add support for +flagm feature for -march in Armv8.4 AArch64.
 
 * Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic
   64-byte load/store instructions for this feature.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9ae0727..ca29fdc 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -9225,6 +9225,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_ARCH_NONE},
   {"ls64",		AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0),
 			AARCH64_ARCH_NONE},
+  {"flagm",		AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 526e808..c005286 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -226,6 +226,12 @@ automatically cause those extensions to be disabled.
  @code{pmullt} and @code{pmullb} instructions.
 @item @code{sve2-sha3} @tab ARMv8-A @tab No
  @tab Enable SVE2 SHA3 Extension.
+@item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
+ @tab Enable Flag Manipulation instructions.
+@item @code{csre} @tab ARMv8-A @tab No
+ @tab Enable Call Stack Recorder Extension.
+@item @code{ls64} @tab ARMv8-6 @tab ARMv8.7-A or later
+ @tab Enable 64 Byte Loads/Stores.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/flagm.d b/gas/testsuite/gas/aarch64/flagm.d
new file mode 100644
index 0000000..2f993bb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/flagm.d
@@ -0,0 +1,16 @@
+#name: FLAGM (Condition flag manipulation) feature
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d500401f 	cfinv
+.*:	ba0407cf 	rmif	x30, #8, #15
+.*:	3a00080d 	setf8	w0
+.*:	3a00480d 	setf16	w0
+.*:	d500401f 	cfinv
+.*:	ba0407cf 	rmif	x30, #8, #15
+.*:	3a00080d 	setf8	w0
+.*:	3a00480d 	setf16	w0
diff --git a/gas/testsuite/gas/aarch64/flagm.s b/gas/testsuite/gas/aarch64/flagm.s
new file mode 100644
index 0000000..0a54f14
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/flagm.s
@@ -0,0 +1,16 @@
+/* FLAGM (Condition flag manipulation) feature from Armv8.4-A.  */
+.arch armv8.4-a
+
+	cfinv
+	rmif    x30, #8, #15
+	setf8   w0
+	setf16  w0
+
+
+/* FLAGM feature enabled with +flagm.  */
+.arch armv8-a+flagm
+
+	cfinv
+	rmif    x30, #8, #15
+	setf8   w0
+	setf16  w0
diff --git a/include/ChangeLog b/include/ChangeLog
index f54d85d..93d9653 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2020-11-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_FLAGM): Add new feature.
+	(AARCH64_FEATURE_FLAGMANIP): Update comment.
+	(AARCH64_ARCH_V8_4): Add back FLAGM to Armv8.4-A.
+
 2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
 
 	* opcode/pru.h: Add LMBD (left-most bit detect) opcode index.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 304c6cb..aad2c41 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -75,7 +75,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_AES	     (1ULL << 35) /* AES instructions.  */
 #define AARCH64_FEATURE_F16_FML      (1ULL << 36) /* v8.2 FP16FML ins.  */
 #define AARCH64_FEATURE_V8_5	     (1ULL << 37) /* ARMv8.5 processors.  */
-#define AARCH64_FEATURE_FLAGMANIP    (1ULL << 38) /* Flag Manipulation insns.  */
+#define AARCH64_FEATURE_FLAGMANIP    (1ULL << 38) /* v8.5 Flag Manipulation version 2.  */
 #define AARCH64_FEATURE_FRINTTS      (1ULL << 39) /* FRINT[32,64][Z,X] insns.  */
 #define AARCH64_FEATURE_SB	     (1ULL << 40) /* SB instruction.  */
 #define AARCH64_FEATURE_PREDRES      (1ULL << 41) /* Execution and Data Prediction Restriction instructions.  */
@@ -90,6 +90,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_I8MM	     (1ULL << 52) /* Matrix Multiply instructions.  */
 #define AARCH64_FEATURE_F32MM	     (1ULL << 53)
 #define AARCH64_FEATURE_F64MM	     (1ULL << 54)
+#define AARCH64_FEATURE_FLAGM	     (1ULL << 55) /* v8.4 Flag Manipulation.  */
 
 /* Crypto instructions are the combination of AES and SHA2.  */
 #define AARCH64_FEATURE_CRYPTO	(AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
@@ -117,6 +118,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_ARCH_V8_4	AARCH64_FEATURE (AARCH64_ARCH_V8_3,	\
 						 AARCH64_FEATURE_V8_4   \
 						 | AARCH64_FEATURE_DOTPROD \
+						 | AARCH64_FEATURE_FLAGM \
 						 | AARCH64_FEATURE_F16_FML)
 #define AARCH64_ARCH_V8_5	AARCH64_FEATURE (AARCH64_ARCH_V8_4,	\
 						 AARCH64_FEATURE_V8_5   \
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b25132a..1e7e40f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2020-11-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+	* aarch64-tbl.h (FLAGM): Handle for FLAGM feature.
+	(struct aarch64_opcode):  Move FLAGM instructions from V8_4_INSN to
+	FLAGM_INSN.
+	(AARCH64_FEATURE_FLAGMANIP): Update comment for FEAT_FlagM2.
+
 2020-11-14  Borislav Petkov  <bp@suse.de>
 
 	* i386-dis.c (ckprefix): Do not assign active_seg_prefix in
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 2b409dc..c4e9c60 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2422,6 +2422,8 @@ static const aarch64_feature_set aarch64_feature_csre =
   AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0);
 static const aarch64_feature_set aarch64_feature_ls64 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_6 | AARCH64_FEATURE_LS64, 0);
+static const aarch64_feature_set aarch64_feature_flagm =
+  AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2470,6 +2472,7 @@ static const aarch64_feature_set aarch64_feature_ls64 =
 #define ARMV8_7	  &aarch64_feature_v8_7
 #define CSRE	  &aarch64_feature_csre
 #define LS64	  &aarch64_feature_ls64
+#define FLAGM	  &aarch64_feature_flagm
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2583,6 +2586,8 @@ static const aarch64_feature_set aarch64_feature_ls64 =
   { NAME, OPCODE, MASK, CLASS, 0, CSRE, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 struct aarch64_opcode aarch64_opcode_table[] =
 {
@@ -3906,7 +3911,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
      potentially alias with too many instructions and so the tree can't be constructed.   As a work
      around we just place cfinv before msr.  This means the order between these two shouldn't be
      changed.  */
-  V8_4_INSN ("cfinv",  0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
+  FLAGM_INSN ("cfinv",  0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
   CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
   CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
   CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
@@ -5084,9 +5089,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
   FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
   FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
   /* System extensions ARMv8.4-a.  */
-  V8_4_INSN ("rmif",   0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
-  V8_4_INSN ("setf8",  0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
-  V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
+  FLAGM_INSN ("rmif",   0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
+  FLAGM_INSN ("setf8",  0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
+  FLAGM_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
   /* Memory access instructions ARMv8.4-a.  */
   V8_4_INSN ("stlurb" ,  0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
   V8_4_INSN ("ldapurb",  0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),