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| author | Mike Frysinger <vapier@gentoo.org> | 2022-11-07 23:44:36 +0700 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2022-11-07 23:44:36 +0700 |
| commit | 4faede6126762a9704da4c79093cca15c15efafa (patch) | |
| tree | cf37891c248f0fae4a34d10a8571e3f3dd12ce32 | |
| parent | 871aa3b9ee7b1067bffa05549190c6051cf06fe5 (diff) | |
| download | gdb-4faede6126762a9704da4c79093cca15c15efafa.zip gdb-4faede6126762a9704da4c79093cca15c15efafa.tar.gz gdb-4faede6126762a9704da4c79093cca15c15efafa.tar.bz2 | |
sim: riscv: add missing AC_MSG_RESULT call
Previous commit in here forgot to include this.
| -rwxr-xr-x | sim/configure | 2 | ||||
| -rw-r--r-- | sim/riscv/acinclude.m4 | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/sim/configure b/sim/configure index e25d60c..1916e1d 100755 --- a/sim/configure +++ b/sim/configure @@ -16279,6 +16279,8 @@ case $target in #( *) : ;; esac +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SIM_RISCV_BITSIZE" >&5 +$as_echo "$SIM_RISCV_BITSIZE" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether sim rx should be cycle accurate" >&5 diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4 index 29dcaeb..0a421f4 100644 --- a/sim/riscv/acinclude.m4 +++ b/sim/riscv/acinclude.m4 @@ -18,4 +18,5 @@ AC_MSG_CHECKING([riscv bitsize]) SIM_RISCV_BITSIZE=64 AS_CASE([$target], [riscv32*], [SIM_RISCV_BITSIZE=32]) +AC_MSG_RESULT([$SIM_RISCV_BITSIZE]) AC_SUBST(SIM_RISCV_BITSIZE) |