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| author | Richard Earnshaw <richard.earnshaw@arm.com> | 2009-02-23 14:58:34 +0000 |
|---|---|---|
| committer | Richard Earnshaw <richard.earnshaw@arm.com> | 2009-02-23 14:58:34 +0000 |
| commit | 4ce8808b2c5fa1b487af90a65e915995c6a76715 (patch) | |
| tree | d111e284d0c86b21501a2d7b471bcd2f8d636f70 | |
| parent | 11c19e16a25eadc2035bc7aafb4587774a1964bf (diff) | |
| download | gdb-4ce8808b2c5fa1b487af90a65e915995c6a76715.zip gdb-4ce8808b2c5fa1b487af90a65e915995c6a76715.tar.gz gdb-4ce8808b2c5fa1b487af90a65e915995c6a76715.tar.bz2 | |
* arm-dis.c (neon_opcodes): Correct bit-mask and patterns for
vq{r}shr{u}n.s64 insnstructions.
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 8 |
2 files changed, 9 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d1a0ada..0f4a65b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2009-02-23 Richard Earnshaw <rearnsha@arm.com> + + * arm-dis.c (neon_opcodes): Correct bit-mask and patterns for + vq{r}shr{u}n.s64 insnstructions. + 2009-02-19 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 44c2383..aedc9f2 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -651,10 +651,10 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, |