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authorJeff Law <jeffreyalaw@gmail.com>2022-03-29 20:05:51 -0400
committerJeff Law <jeffreyalaw@gmail.com>2022-03-29 20:08:35 -0400
commit5321c31bc78379a33f07dc7bef9256d05b942ad7 (patch)
tree6b645d1443adc5e72097b29fec1a9f584c60b6a7
parentc09115ad6e3531be5fc779098a093605622b161e (diff)
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Fix for MUL instruction on the v850
* sim/v850/simops.c (Multiply64): Properly test if we need to negate either of the operands. * sim/testsuite/v850/mul.cgs: New test.
-rw-r--r--sim/testsuite/v850/mul.cgs15
-rw-r--r--sim/v850/simops.c4
2 files changed, 17 insertions, 2 deletions
diff --git a/sim/testsuite/v850/mul.cgs b/sim/testsuite/v850/mul.cgs
new file mode 100644
index 0000000..7d19b70
--- /dev/null
+++ b/sim/testsuite/v850/mul.cgs
@@ -0,0 +1,15 @@
+# v850e mul
+# mach: v850e
+# as(v850e): -mv850e
+
+ .include "testutils.inc"
+
+# Trivial regression test for incorrect sign bit handling in mul
+
+ seti -10, r1
+ seti 2, r2
+ mul r1, r2, r3
+ reg r2, -20
+ reg r3, -1
+
+ pass
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 8fac8bd..d264057 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -339,10 +339,10 @@ Multiply64 (int sign, unsigned long op0)
sign = (op0 ^ op1) & 0x80000000;
- if (((signed long) op0) < 0)
+ if (op0 & 0x80000000)
op0 = - op0;
- if (((signed long) op1) < 0)
+ if (op1 & 0x80000000)
op1 = - op1;
}