[PATCH][ARM][GAS]: Support to MVE VCTP instruction.

This patch adds support for MVE VCTP instruction in assembler.

gas ChangeLog:

2019-09-10  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

        * config/tc-arm.c (M_MNEM_vctp): Add new Mnemonic.
        (do_mve_vctp): Add function to encode VCTP instruction.
        * testsuite/gas/arm/mve-vctp-bad.d: New test.
        * testsuite/gas/arm/mve-vctp-bad.l: Likewise.
        * testsuite/gas/arm/mve-vctp-bad.s: Likewise.
        * testsuite/gas/arm/mve-vctp.d: Likewise.
        * testsuite/gas/arm/mve-vctp.s: Likewise.

6 files changed, 177 insertions, 0 deletions

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 9273bb5..32a15f6 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -14424,6 +14424,7 @@ do_mve_scalar_shift (void)
 #define M_MNEM_vmlsdavax  0xeef01e21
 #define M_MNEM_vmullt	0xee011e00
 #define M_MNEM_vmullb	0xee010e00
+#define M_MNEM_vctp	0xf000e801
 #define M_MNEM_vst20	0xfc801e00
 #define M_MNEM_vst21	0xfc801e20
 #define M_MNEM_vst40	0xfc801e01
@@ -15793,6 +15794,45 @@ mve_get_vcmp_vpt_cond (struct neon_type_el et)
   abort ();
 }
 
+/* For VCTP (create vector tail predicate) in MVE.  */
+static void
+do_mve_vctp (void)
+{
+  int dt = 0;
+  unsigned size = 0x0;
+
+  if (inst.cond > COND_ALWAYS)
+    inst.pred_insn_type = INSIDE_VPT_INSN;
+  else
+    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+  /* This is a typical MVE instruction which has no type but have size 8, 16,
+     32 and 64.  For instructions with no type, inst.vectype.el[j].type is set
+     to NT_untyped and size is updated in inst.vectype.el[j].size.  */
+  if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped))
+    dt = inst.vectype.el[0].size;
+
+  /* Setting this does not indicate an actual NEON instruction, but only
+     indicates that the mnemonic accepts neon-style type suffixes.  */
+  inst.is_neon = 1;
+
+  switch (dt)
+    {
+      case 8:
+	break;
+      case 16:
+	size = 0x1; break;
+      case 32:
+	size = 0x2; break;
+      case 64:
+	size = 0x3; break;
+      default:
+	first_error (_("Type is not allowed for this instruction"));
+    }
+  inst.instruction |= size << 20;
+  inst.instruction |= inst.operands[0].reg << 16;
+}
+
 static void
 do_mve_vpt (void)
 {
@@ -25494,6 +25534,7 @@ static const struct asm_opcode insns[] =
 
  /* MVE and MVE FP only.  */
  mToC("vhcadd",	ee000f00,   4, (RMQ, RMQ, RMQ, EXPi),		  mve_vhcadd),
+ mCEF(vctp,	_vctp,      1, (RRnpc),				  mve_vctp),
  mCEF(vadc,	_vadc,      3, (RMQ, RMQ, RMQ),			  mve_vadc),
  mCEF(vadci,	_vadci,     3, (RMQ, RMQ, RMQ),			  mve_vadc),
  mToC("vsbc",	fe300f00,   3, (RMQ, RMQ, RMQ),			  mve_vsbc),
diff --git a/gas/testsuite/gas/arm/mve-vctp-bad.d b/gas/testsuite/gas/arm/mve-vctp-bad.d
new file mode 100644
index 0000000..b85f9f2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vctp-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid MVE vctp instruction
+#source: mve-vctp-bad.s
+#as: -march=armv8.1-m.main+mve.fp -mfloat-abi=hard
+#error_output: mve-vctp-bad.l
diff --git a/gas/testsuite/gas/arm/mve-vctp-bad.l b/gas/testsuite/gas/arm/mve-vctp-bad.l
new file mode 100644
index 0000000..70e99dd
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vctp-bad.l
@@ -0,0 +1,36 @@
+[^:]*: Assembler messages:
+[^:]*:8: Error: Type is not allowed for this instruction -- `vctp.s8 r13'
+[^:]*:8: Error: Type is not allowed for this instruction -- `vctp.u16 r13'
+[^:]*:8: Error: Type is not allowed for this instruction -- `vctp.f32 r13'
+[^:]*:8: Error: r15 not allowed here -- `vctp.8 r15'
+[^:]*:8: Error: r15 not allowed here -- `vctp.16 r15'
+[^:]*:8: Error: r15 not allowed here -- `vctp.32 r15'
+[^:]*:8: Error: r15 not allowed here -- `vctp.64 r15'
+[^:]*:8: Error: r15 not allowed here -- `vctp.s8 r15'
+[^:]*:8: Error: r15 not allowed here -- `vctp.u16 r15'
+[^:]*:8: Error: r15 not allowed here -- `vctp.f32 r15'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r0'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r0'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r0'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r0'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r0'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r1'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r1'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r1'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r1'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r1'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r2'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r2'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r2'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r2'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r2'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r4'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r4'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r4'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r4'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r4'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.8 r8'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.16 r8'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.32 r8'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.64 r8'
+[^:]*:14: Error: vector predicated instruction should be in VPT/VPST block -- `vctpt.f32 r8'
diff --git a/gas/testsuite/gas/arm/mve-vctp-bad.s b/gas/testsuite/gas/arm/mve-vctp-bad.s
new file mode 100644
index 0000000..217d75d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vctp-bad.s
@@ -0,0 +1,14 @@
+.syntax unified
+.thumb
+
+.irp op1, r13, r15
+.irp op2 8, 16, 32, 64, s8, u16, f32
+vctp.\op2 \op1
+.endr
+.endr
+
+.irp op1, r0, r1, r2, r4, r8
+.irp op2 8, 16, 32, 64, f32
+vctpt.\op2 \op1
+.endr
+.endr
diff --git a/gas/testsuite/gas/arm/mve-vctp.d b/gas/testsuite/gas/arm/mve-vctp.d
new file mode 100644
index 0000000..e9ec138
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vctp.d
@@ -0,0 +1,67 @@
+# name: MVE vctp instructions
+# as: -march=armv8.1-m.main+mve
+# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^>]*> f000 e801 	vctp.8	r0
+[^>]*> f010 e801 	vctp.16	r0
+[^>]*> f020 e801 	vctp.32	r0
+[^>]*> f030 e801 	vctp.64	r0
+[^>]*> f001 e801 	vctp.8	r1
+[^>]*> f011 e801 	vctp.16	r1
+[^>]*> f021 e801 	vctp.32	r1
+[^>]*> f031 e801 	vctp.64	r1
+[^>]*> f002 e801 	vctp.8	r2
+[^>]*> f012 e801 	vctp.16	r2
+[^>]*> f022 e801 	vctp.32	r2
+[^>]*> f032 e801 	vctp.64	r2
+[^>]*> f004 e801 	vctp.8	r4
+[^>]*> f014 e801 	vctp.16	r4
+[^>]*> f024 e801 	vctp.32	r4
+[^>]*> f034 e801 	vctp.64	r4
+[^>]*> f008 e801 	vctp.8	r8
+[^>]*> f018 e801 	vctp.16	r8
+[^>]*> f028 e801 	vctp.32	r8
+[^>]*> f038 e801 	vctp.64	r8
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f000 e801 	vctpt.8	r0
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f010 e801 	vctpt.16	r0
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f020 e801 	vctpt.32	r0
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f030 e801 	vctpt.64	r0
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f001 e801 	vctpt.8	r1
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f011 e801 	vctpt.16	r1
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f021 e801 	vctpt.32	r1
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f031 e801 	vctpt.64	r1
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f002 e801 	vctpt.8	r2
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f012 e801 	vctpt.16	r2
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f022 e801 	vctpt.32	r2
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f032 e801 	vctpt.64	r2
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f004 e801 	vctpt.8	r4
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f014 e801 	vctpt.16	r4
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f024 e801 	vctpt.32	r4
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f034 e801 	vctpt.64	r4
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f008 e801 	vctpt.8	r8
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f018 e801 	vctpt.16	r8
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f028 e801 	vctpt.32	r8
+[^>]*> fe71 0f4d 	vpst
+[^>]*> f038 e801 	vctpt.64	r8
diff --git a/gas/testsuite/gas/arm/mve-vctp.s b/gas/testsuite/gas/arm/mve-vctp.s
new file mode 100644
index 0000000..b00ca5a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vctp.s
@@ -0,0 +1,15 @@
+.syntax unified
+.thumb
+
+.irp op1, r0, r1, r2, r4, r8
+.irp op2 8, 16, 32, 64
+vctp.\op2 \op1
+.endr
+.endr
+
+.irp op1, r0, r1, r2, r4, r8
+.irp op2 8, 16, 32, 64
+vpst
+vctpt.\op2 \op1
+.endr
+.endr