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author | Mike Frysinger <vapier@gentoo.org> | 2011-06-04 13:06:39 -0400 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2024-01-01 18:23:25 -0500 |
commit | a3a35fa65a0e493804fb4ae02cd90ec40694d870 (patch) | |
tree | dbdf8dfd122598cdde1858fcb96ce2f2d06cb165 | |
parent | b295d144aeeeb50843beb850536dcd6d7ae0a312 (diff) | |
download | gdb-a3a35fa65a0e493804fb4ae02cd90ec40694d870.zip gdb-a3a35fa65a0e493804fb4ae02cd90ec40694d870.tar.gz gdb-a3a35fa65a0e493804fb4ae02cd90ec40694d870.tar.bz2 |
sim: bfin: add proper regs to dmac
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
-rw-r--r-- | sim/bfin/dv-bfin_dmac.c | 44 | ||||
-rw-r--r-- | sim/bfin/machs.c | 2 | ||||
-rw-r--r-- | sim/bfin/machs.h | 1 |
3 files changed, 47 insertions, 0 deletions
diff --git a/sim/bfin/dv-bfin_dmac.c b/sim/bfin/dv-bfin_dmac.c index b193dc3..5480dcb 100644 --- a/sim/bfin/dv-bfin_dmac.c +++ b/sim/bfin/dv-bfin_dmac.c @@ -37,7 +37,21 @@ struct bfin_dmac const char * const *pmap; unsigned int pmap_count; + + /* Order after here is important -- matches hardware MMR layout. */ + bu32 _pad0[3]; + bu16 BFIN_MMR_16 (tc_per); + bu16 BFIN_MMR_16 (tc_cnt); +}; +#define mmr_base() offsetof(struct bfin_dmac, _pad0[0]) +#define mmr_offset(mmr) (offsetof(struct bfin_dmac, mmr) - mmr_base()) +#define mmr_idx(mmr) (mmr_offset (mmr) / 4) + +static const char * const mmr_names[] = +{ + [mmr_idx (tc_per)] = "DMAC_TC_PER", "DMAC_TC_CNT", }; +#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") struct hw * bfin_dmac_get_peer (struct hw *dma, bu16 pmap) @@ -372,6 +386,34 @@ bfin_dmac_port_event (struct hw *me, int my_port, struct hw *source, } static void +attach_bfin_dmac_regs (struct hw *me, struct bfin_dmac *dmac) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_DMAC_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_DMAC_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + dmac->base = attach_address; +} + +static void bfin_dmac_finish (struct hw *me) { struct bfin_dmac *dmac; @@ -382,6 +424,8 @@ bfin_dmac_finish (struct hw *me) set_hw_data (me, dmac); set_hw_port_event (me, bfin_dmac_port_event); + attach_bfin_dmac_regs (me, dmac); + /* Initialize the DMA Controller. */ if (hw_find_property (me, "type") == NULL) hw_abort (me, "Missing \"type\" property"); diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c index 92ce85a..4ed4c0d 100644 --- a/sim/bfin/machs.c +++ b/sim/bfin/machs.c @@ -655,6 +655,7 @@ static const struct bfin_dev_layout bf534_dev[] = DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC00B00, BFIN_MMR_DMAC_SIZE, "bfin_dmac@0"), DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), @@ -690,6 +691,7 @@ static const struct bfin_dev_layout bf537_dev[] = DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"), DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"), + DEVICE (0xFFC00B00, BFIN_MMR_DMAC_SIZE, "bfin_dmac@0"), DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"), DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"), DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"), diff --git a/sim/bfin/machs.h b/sim/bfin/machs.h index 5bddfcf..e062cc0 100644 --- a/sim/bfin/machs.h +++ b/sim/bfin/machs.h @@ -52,6 +52,7 @@ extern const SIM_MACH * const bfin_sim_machs[]; #define BFIN_COREMMR_WP_SIZE 0x204 #define BFIN_MMR_DMA_SIZE (4 * 16) +#define BFIN_MMR_DMAC_SIZE 0x20 #define BFIN_MMR_DMAC0_BASE 0xFFC00C00 #define BFIN_MMR_DMAC1_BASE 0xFFC01C00 #define BFIN_MMR_EBIU_AMC_SIZE (4 * 3) |