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authorAlan Modra <amodra@gmail.com>2020-01-20 12:31:58 +1030
committerAlan Modra <amodra@gmail.com>2020-01-20 15:45:50 +1030
commit2bddb71a7421213dd9d8b8f2db133b43f5e1357e (patch)
treefcad008cb31d002d4d2289e904fca5d7494711ea
parentcf1d9e092f871df3b34a58cfcde915c689ac9067 (diff)
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ubsan: arm: out of bounds array access
.inst 0x81bdfe9f disassembles as 0: 81bdfe9f ldaexdhi pc, reg-names-std, [sp] I'm quite sure "reg-names-std" isn't an ARM register. * arm-dis.c (print_insn_arm): Wrap 'T' value.
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/arm-dis.c2
2 files changed, 5 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1f71751..04eaa86 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-01-20 Alan Modra <amodra@gmail.com>
+
+ * arm-dis.c (print_insn_arm): Wrap 'T' value.
+
2020-01-18 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index c986b58..be2a932 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -10106,7 +10106,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
case 'T':
/* We want register + 1 when decoding T. */
if (*c == 'T')
- ++value;
+ value = (value + 1) & 0xf;
if (c[1] == 'u')
{