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authorAlex Coplan <alex.coplan@arm.com>2020-09-24 10:10:52 +0100
committerAlex Coplan <alex.coplan@arm.com>2020-09-24 10:10:52 +0100
commitf3034e25fa98d44b775970f40c9ec85eeae096e6 (patch)
tree99e8c93d8c294137dda8dd04c0c8e0c7c160979a
parent81d54bb7aec30fa09ee564c9a51765dc7c019799 (diff)
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arm: Add support for Neoverse N2 CPU
This adds support for Arm's Neoverse N2 CPU to AArch32 binutils. The Neoverse N2 CPU builds AArch32 at EL0 and therefore needs support in the AArch32 assembler. gas/ChangeLog: 2020-09-24 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (arm_cpus): Add Neoverse N2. * doc/c-arm.texi: Document -mcpu=neoverse-n2.
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-arm.c5
-rw-r--r--gas/doc/c-arm.texi1
3 files changed, 11 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 02e6300..30e4e34 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-09-24 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add Neoverse N2.
+ * doc/c-arm.texi: Document -mcpu=neoverse-n2.
+
2020-09-24 Lili Cui <lili.cui@intel.com>
* NEWS: Add TDX.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 32feaa1..fce3ad3 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -31594,6 +31594,11 @@ static const struct arm_cpu_option_table arm_cpus[] =
ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
+ ARM_CPU_OPT ("neoverse-n2", "Neoverse N2", ARM_ARCH_V8_5A,
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
+ | ARM_EXT2_BF16
+ | ARM_EXT2_I8MM),
+ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
/* ??? XSCALE is really an architecture. */
ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
ARM_ARCH_NONE,
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 9180360..39e24e7 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -151,6 +151,7 @@ recognized:
@code{marvell-pj4},
@code{marvell-whitney},
@code{neoverse-n1},
+@code{neoverse-n2},
@code{xgene1},
@code{xgene2},
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),