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authorDoug Evans <dje@google.com>1998-02-23 21:20:37 +0000
committerDoug Evans <dje@google.com>1998-02-23 21:20:37 +0000
commit0bf55db8fd2e1022e91392223925e93541da72be (patch)
tree370a5fd9770973e32af94cd651ab72ae3861c7a6
parentb1f09b637ef5cb8f67b34924f64488b4e2cfc437 (diff)
downloadgdb-0bf55db8fd2e1022e91392223925e93541da72be.zip
gdb-0bf55db8fd2e1022e91392223925e93541da72be.tar.gz
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* m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate.
Diffstat
-rw-r--r--opcodes/ChangeLog2
-rw-r--r--opcodes/m32r-asm.c349
-rw-r--r--opcodes/m32r-dis.c33
-rw-r--r--opcodes/m32r-opc.c1035
-rw-r--r--opcodes/m32r-opc.h8
5 files changed, 738 insertions, 689 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9b3b25e..9a16464 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -3,6 +3,8 @@ Mon Feb 23 13:16:17 1998 Doug Evans <devans@seba.cygnus.com>
* cgen-asm.c: Include symcat.h.
* cgen-dis.c,cgen-opc.c,cgen-asm.in,cgen-dis.in: Ditto.
+ * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate.
+
start-sanitize-sky
Mon Feb 23 09:51:39 1998 Doug Evans <devans@canuck.cygnus.com>
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index 318fa2d..27f5ea9 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -3,7 +3,7 @@
This file is used to generate m32r-asm.c.
-Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
This file is part of the GNU Binutils and GDB, the GNU debugger.
@@ -26,6 +26,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include "ansidecl.h"
#include "bfd.h"
+#include "symcat.h"
#include "m32r-opc.h"
/* ??? The layout of this stuff is still work in progress.
@@ -37,34 +38,64 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
static const char * parse_insn_normal
PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *));
-static void insert_insn_normal
+static const char * insert_insn_normal
PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *));
/* Default insertion routine.
- SHIFT is negative for left shifts, positive for right shifts.
- All bits of VALUE to be inserted must be valid as we don't handle
- signed vs unsigned shifts.
+ ATTRS is a mask of the boolean attributes.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn (currently 8,16,32).
- ATTRS is a mask of the boolean attributes. We don't need any at the
- moment, but for consistency with extract_normal we have them. */
+ The result is an error message or NULL if success. */
-/* FIXME: This duplicates functionality with bfd's howto table and
+/* ??? This duplicates functionality with bfd's howto table and
bfd_install_relocation. */
-/* FIXME: For architectures where insns can be representable as ints,
- store insn in `field' struct and add registers, etc. while parsing. */
+/* ??? For architectures where insns can be representable as ints,
+ store insn in `field' struct and add registers, etc. while parsing? */
-static CGEN_INLINE void
+static const char *
insert_normal (value, attrs, start, length, shift, total_length, buffer)
- long value;
+ long value;
unsigned int attrs;
- int start;
- int length;
- int shift;
- int total_length;
- char * buffer;
+ int start;
+ int length;
+ int shift;
+ int total_length;
+ char * buffer;
{
bfd_vma x;
+ static char buf[100];
+
+ if (shift < 0)
+ value <<= -shift;
+ else
+ value >>= shift;
+
+ /* Ensure VALUE will fit. */
+ if ((attrs & (1 << CGEN_OPERAND_UNSIGNED)) != 0)
+ {
+ unsigned long max = (1 << length) - 1;
+ if ((unsigned long) value > max)
+ {
+ const char *err = "operand out of range (%lu not between 0 and %lu)";
+
+ sprintf (buf, err, value, max);
+ return buf;
+ }
+ }
+ else
+ {
+ long min = - (1 << (length - 1));
+ long max = (1 << (length - 1)) - 1;
+ if (value < min || value > max)
+ {
+ const char *err = "operand out of range (%ld not between %ld and %ld)";
+
+ sprintf (buf, err, value, min, max);
+ return buf;
+ }
+ }
#if 0 /*def CGEN_INT_INSN*/
*buffer |= ((value & ((1 << length) - 1))
@@ -91,11 +122,6 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer)
abort ();
}
- if (shift < 0)
- value <<= -shift;
- else
- value >>= shift;
-
x |= ((value & ((1 << length) - 1))
<< (total_length - (start + length)));
@@ -120,6 +146,8 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer)
abort ();
}
#endif
+
+ return NULL;
}
/* -- assembler routines inserted here */
@@ -128,10 +156,9 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer)
/* Handle shigh(), high(). */
static const char *
-parse_h_hi16 (strp, opindex, min, max, valuep)
+parse_h_hi16 (strp, opindex, valuep)
const char **strp;
int opindex;
- unsigned long min, max;
unsigned long *valuep;
{
const char *errmsg;
@@ -168,7 +195,7 @@ parse_h_hi16 (strp, opindex, min, max, valuep)
return errmsg;
}
- return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
+ return cgen_parse_unsigned_integer (strp, opindex, valuep);
}
/* Handle low() in a signed context. Also handle sda().
@@ -176,10 +203,9 @@ parse_h_hi16 (strp, opindex, min, max, valuep)
handles the case where low() isn't present. */
static const char *
-parse_h_slo16 (strp, opindex, min, max, valuep)
+parse_h_slo16 (strp, opindex, valuep)
const char **strp;
int opindex;
- long min, max;
long *valuep;
{
const char *errmsg;
@@ -197,6 +223,9 @@ parse_h_slo16 (strp, opindex, min, max, valuep)
if (**strp != ')')
return "missing `)'";
++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ *valuep &= 0xffff;
return errmsg;
}
@@ -210,7 +239,7 @@ parse_h_slo16 (strp, opindex, min, max, valuep)
return errmsg;
}
- return cgen_parse_signed_integer (strp, opindex, min, max, valuep);
+ return cgen_parse_signed_integer (strp, opindex, valuep);
}
/* Handle low() in an unsigned context.
@@ -218,10 +247,9 @@ parse_h_slo16 (strp, opindex, min, max, valuep)
handles the case where low() isn't present. */
static const char *
-parse_h_ulo16 (strp, opindex, min, max, valuep)
+parse_h_ulo16 (strp, opindex, valuep)
const char **strp;
int opindex;
- unsigned long min, max;
unsigned long *valuep;
{
const char *errmsg;
@@ -239,10 +267,13 @@ parse_h_ulo16 (strp, opindex, min, max, valuep)
if (**strp != ')')
return "missing `)'";
++*strp;
+ if (errmsg == NULL
+ && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+ *valuep &= 0xffff;
return errmsg;
}
- return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep);
+ return cgen_parse_unsigned_integer (strp, opindex, valuep);
}
/* -- */
@@ -261,7 +292,7 @@ parse_h_ulo16 (strp, opindex, min, max, valuep)
the handlers.
*/
-CGEN_INLINE const char *
+const char *
m32r_cgen_parse_operand (opindex, strp, fields)
int opindex;
const char ** strp;
@@ -290,23 +321,23 @@ m32r_cgen_parse_operand (opindex, strp, fields)
errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, & fields->f_r1);
break;
case M32R_OPERAND_SIMM8 :
- errmsg = cgen_parse_signed_integer (strp, 7, -128, 127, &fields->f_simm8);
+ errmsg = cgen_parse_signed_integer (strp, M32R_OPERAND_SIMM8, &fields->f_simm8);
break;
case M32R_OPERAND_SIMM16 :
- errmsg = cgen_parse_signed_integer (strp, 8, -32768, 32767, &fields->f_simm16);
+ errmsg = cgen_parse_signed_integer (strp, M32R_OPERAND_SIMM16, &fields->f_simm16);
break;
case M32R_OPERAND_UIMM4 :
- errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 15, &fields->f_uimm4);
+ errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM4, &fields->f_uimm4);
break;
case M32R_OPERAND_UIMM5 :
- errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 31, &fields->f_uimm5);
+ errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM5, &fields->f_uimm5);
break;
case M32R_OPERAND_UIMM16 :
- errmsg = cgen_parse_unsigned_integer (strp, 11, 0, 65535, &fields->f_uimm16);
+ errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM16, &fields->f_uimm16);
break;
/* start-sanitize-m32rx */
case M32R_OPERAND_IMM1 :
- errmsg = cgen_parse_unsigned_integer (strp, 12, 0, 1, &fields->f_imm1);
+ errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_IMM1, &fields->f_imm1);
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
@@ -325,25 +356,25 @@ m32r_cgen_parse_operand (opindex, strp, fields)
break;
/* end-sanitize-m32rx */
case M32R_OPERAND_HI16 :
- errmsg = parse_h_hi16 (strp, 16, 0, 65535, &fields->f_hi16);
+ errmsg = parse_h_hi16 (strp, M32R_OPERAND_HI16, &fields->f_hi16);
break;
case M32R_OPERAND_SLO16 :
- errmsg = parse_h_slo16 (strp, 17, -32768, 32767, &fields->f_simm16);
+ errmsg = parse_h_slo16 (strp, M32R_OPERAND_SLO16, &fields->f_simm16);
break;
case M32R_OPERAND_ULO16 :
- errmsg = parse_h_ulo16 (strp, 18, 0, 65535, &fields->f_uimm16);
+ errmsg = parse_h_ulo16 (strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
break;
case M32R_OPERAND_UIMM24 :
- errmsg = cgen_parse_address (strp, 19, 0, NULL, & fields->f_uimm24);
+ errmsg = cgen_parse_address (strp, M32R_OPERAND_UIMM24, 0, NULL, & fields->f_uimm24);
break;
case M32R_OPERAND_DISP8 :
- errmsg = cgen_parse_address (strp, 20, 0, NULL, & fields->f_disp8);
+ errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP8, 0, NULL, & fields->f_disp8);
break;
case M32R_OPERAND_DISP16 :
- errmsg = cgen_parse_address (strp, 21, 0, NULL, & fields->f_disp16);
+ errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP16, 0, NULL, & fields->f_disp16);
break;
case M32R_OPERAND_DISP24 :
- errmsg = cgen_parse_address (strp, 22, 0, NULL, & fields->f_disp24);
+ errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP24, 0, NULL, & fields->f_disp24);
break;
default :
@@ -369,191 +400,105 @@ m32r_cgen_parse_operand (opindex, strp, fields)
resolved during parsing.
*/
-CGEN_INLINE void
+const char *
m32r_cgen_insert_operand (opindex, fields, buffer)
int opindex;
CGEN_FIELDS * fields;
- cgen_insn_t * buffer;
-{
- switch (opindex)
- {
- case M32R_OPERAND_SR :
- insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_DR :
- insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_SRC1 :
- insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_SRC2 :
- insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_SCR :
- insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_DCR :
- insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_SIMM8 :
- insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_SIMM16 :
- insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_UIMM4 :
- insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_UIMM5 :
- insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_UIMM16 :
- insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
-/* start-sanitize-m32rx */
- case M32R_OPERAND_IMM1 :
- insert_normal (fields->f_imm1, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- case M32R_OPERAND_ACCD :
- insert_normal (fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- case M32R_OPERAND_ACCS :
- insert_normal (fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- case M32R_OPERAND_ACC :
- insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
-/* end-sanitize-m32rx */
- case M32R_OPERAND_HI16 :
- insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_SLO16 :
- insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_ULO16 :
- insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_UIMM24 :
- insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_DISP8 :
- insert_normal (fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_DISP16 :
- insert_normal (fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
- case M32R_OPERAND_DISP24 :
- insert_normal (fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
- break;
-
- default :
- fprintf (stderr, "Unrecognized field %d while building insn.\n",
- opindex);
- abort ();
- }
-}
-
-/* Main entry point for operand validation.
-
- This function is called from GAS when it has fully resolved an operand
- that couldn't be resolved during parsing.
-
- The result is NULL for success or an error message (which may be
- computed into a static buffer).
-*/
-
-CGEN_INLINE const char *
-m32r_cgen_validate_operand (opindex, fields)
- int opindex;
- const CGEN_FIELDS * fields;
+ char * buffer;
{
- const char * errmsg = NULL;
+ const char * errmsg;
switch (opindex)
{
case M32R_OPERAND_SR :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_DR :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_SRC1 :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_SRC2 :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_SCR :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_DCR :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_SIMM8 :
- errmsg = cgen_validate_signed_integer (fields->f_simm8, -128, 127);
+ errmsg = insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_SIMM16 :
- errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
+ errmsg = insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_UIMM4 :
- errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15);
+ errmsg = insert_normal (fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_UIMM5 :
- errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31);
+ errmsg = insert_normal (fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_UIMM16 :
- errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
+ errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
/* start-sanitize-m32rx */
case M32R_OPERAND_IMM1 :
- errmsg = cgen_validate_unsigned_integer (fields->f_imm1, 0, 1);
+ {
+ long value = ((fields->f_imm1) - (1));
+ errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCD :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCS :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACC :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
/* end-sanitize-m32rx */
case M32R_OPERAND_HI16 :
- errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535);
+ errmsg = insert_normal (fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_SLO16 :
- errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767);
+ errmsg = insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_ULO16 :
- errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535);
+ errmsg = insert_normal (fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_UIMM24 :
- /* nothing to do */
+ errmsg = insert_normal (fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
case M32R_OPERAND_DISP8 :
- /* nothing to do */
+ {
+ long value = ((fields->f_disp8) >> (2));
+ errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
break;
case M32R_OPERAND_DISP16 :
- /* nothing to do */
+ {
+ long value = ((fields->f_disp16) >> (2));
+ errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
break;
case M32R_OPERAND_DISP24 :
- /* nothing to do */
+ {
+ long value = ((fields->f_disp24) >> (2));
+ errmsg = insert_normal (value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ }
break;
default :
- fprintf (stderr, "Unrecognized field %d while validating operand.\n",
+ fprintf (stderr, "Unrecognized field %d while building insn.\n",
opindex);
abort ();
}
@@ -600,17 +545,17 @@ m32r_cgen_init_asm (mach, endian)
static const char *
parse_insn_normal (insn, strp, fields)
- const CGEN_INSN * insn;
- const char ** strp;
- CGEN_FIELDS * fields;
+ const CGEN_INSN * insn;
+ const char ** strp;
+ CGEN_FIELDS * fields;
{
- const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
- const char * str = *strp;
- const char * errmsg;
- const char * p;
+ const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
+ const char * str = *strp;
+ const char * errmsg;
+ const char * p;
const unsigned char * syn;
#ifdef CGEN_MNEMONIC_OPERANDS
- int past_opcode_p;
+ int past_opcode_p;
#endif
/* For now we assume the mnemonic is first (there are no leading operands).
@@ -630,13 +575,13 @@ parse_insn_normal (insn, strp, fields)
/* We don't check for (*str != '\0') here because we want to parse
any trailing fake arguments in the syntax string. */
syn = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
-
+
/* Mnemonics come first for now, ensure valid string. */
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
abort ();
-
+
++syn;
-
+
while (* syn != 0)
{
/* Non operand chars must match exactly. */
@@ -655,7 +600,8 @@ parse_insn_normal (insn, strp, fields)
else
{
/* Syntax char didn't match. Can't be this insn. */
- /* FIXME: would like to return "expected char `c'" */
+ /* FIXME: would like to return something like
+ "expected char `c'" */
return "syntax error";
}
continue;
@@ -692,16 +638,18 @@ parse_insn_normal (insn, strp, fields)
}
/* Default insn builder (insert handler).
- The instruction is recorded in target byte order. */
+ The instruction is recorded in target byte order.
+ The result is an error message or NULL if success. */
+/* FIXME: change buffer to char *? */
-static void
+static const char *
insert_insn_normal (insn, fields, buffer)
- const CGEN_INSN * insn;
- CGEN_FIELDS * fields;
- cgen_insn_t * buffer;
+ const CGEN_INSN * insn;
+ CGEN_FIELDS * fields;
+ cgen_insn_t * buffer;
{
- const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
- bfd_vma value;
+ const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
+ bfd_vma value;
const unsigned char * syn;
CGEN_INIT_INSERT ();
@@ -741,11 +689,18 @@ insert_insn_normal (insn, fields, buffer)
for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
{
+ const char *errmsg;
+
if (CGEN_SYNTAX_CHAR_P (* syn))
continue;
- m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, buffer);
+ errmsg = m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields,
+ (char *) buffer);
+ if (errmsg)
+ return errmsg;
}
+
+ return NULL;
}
/* Main entry point.
@@ -758,12 +713,12 @@ insert_insn_normal (insn, fields, buffer)
const CGEN_INSN *
m32r_cgen_assemble_insn (str, fields, buf, errmsg)
- const char * str;
+ const char * str;
CGEN_FIELDS * fields;
cgen_insn_t * buf;
- char ** errmsg;
+ char ** errmsg;
{
- const char * start;
+ const char * start;
CGEN_INSN_LIST * ilist;
/* Skip leading white space. */
@@ -802,16 +757,10 @@ m32r_cgen_assemble_insn (str, fields, buf, errmsg)
/* FIXME: wip */
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
- /* ??? The extent to which moving the parse and insert handlers into
- this function (thus removing the function call) will speed things up
- is unclear. The simplicity and flexibility of the current scheme is
- appropriate for now. One could have the best of both worlds with
- inline functions but of course that would only work for gcc. Since
- we're machine generating some code we could do that here too. Maybe
- later. */
if (! CGEN_PARSE_FN (insn) (insn, & str, fields))
{
- CGEN_INSERT_FN (insn) (insn, fields, buf);
+ if (CGEN_INSERT_FN (insn) (insn, fields, buf) != NULL)
+ continue;
/* It is up to the caller to actually output the insn and any
queued relocs. */
return insn;
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index 9b467eb..dbe5282 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -26,6 +26,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "ansidecl.h"
#include "dis-asm.h"
#include "bfd.h"
+#include "symcat.h"
#include "m32r-opc.h"
/* ??? The layout of this stuff is still work in progress.
@@ -87,6 +88,8 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length,
value <<= shift;
*valuep = value;
+
+ /* FIXME: for now */
return 1;
}
@@ -194,7 +197,7 @@ my_print_insn (pc, info, buf, buflen)
the handlers.
*/
-CGEN_INLINE int
+int
m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
int opindex;
PTR buf_ctrl;
@@ -240,7 +243,11 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
break;
/* start-sanitize-m32rx */
case M32R_OPERAND_IMM1 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_imm1);
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, 0, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_imm1 = ((value) + (1));
+ }
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
@@ -271,13 +278,25 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm24);
break;
case M32R_OPERAND_DISP8 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_disp8);
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_disp8 = ((value) << (2));
+ }
break;
case M32R_OPERAND_DISP16 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_disp16);
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_disp16 = ((value) << (2));
+ }
break;
case M32R_OPERAND_DISP24 :
- length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_disp24);
+ {
+ long value;
+ length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), & value);
+ fields->f_disp24 = ((value) << (2));
+ }
break;
default :
@@ -303,7 +322,7 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
the handlers.
*/
-CGEN_INLINE void
+void
m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
int opindex;
disassemble_info * info;
@@ -448,7 +467,7 @@ extract_insn_normal (insn, buf_ctrl, insn_value, fields)
continue;
length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn),
- buf_ctrl, insn_value, fields);
+ buf_ctrl, insn_value, fields);
if (length == 0)
return 0;
}
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index b69de02..f42f141 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -314,6 +314,7 @@ static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
+
const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
{
/* pc: program counter */
@@ -399,11 +400,6 @@ const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
/* accum: accumulator */
{ "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
{ 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-/* start-sanitize-m32rx */
-/* abort-parallel-execution: abort parallel execution */
- { "abort-parallel-execution", & HW_ENT (HW_H_ABORT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-/* end-sanitize-m32rx */
};
/* Operand references. */
@@ -908,299 +904,16 @@ static const CGEN_OPERAND_INSTANCE fmt_79_mulwu1_ops[] = {
static const CGEN_OPERAND_INSTANCE fmt_80_sc_ops[] = {
{ INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
- { OUTPUT, & HW_ENT (HW_H_ABORT), CGEN_MODE_UBI, 0, 0 },
{ 0 }
};
#undef INPUT
#undef OUTPUT
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-static const CGEN_SYNTAX syntax_table[] =
-{
-/* <mnem> $dr,$sr */
-/* 0 */ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
-/* <mnem> $dr,$sr,#$slo16 */
-/* 1 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SLO16), 0 },
-/* <mnem> $dr,$sr,$slo16 */
-/* 2 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SLO16), 0 },
-/* <mnem> $dr,$sr,#$uimm16 */
-/* 3 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 },
-/* <mnem> $dr,$sr,$uimm16 */
-/* 4 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
-/* <mnem> $dr,$sr,#$ulo16 */
-/* 5 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (ULO16), 0 },
-/* <mnem> $dr,$sr,$ulo16 */
-/* 6 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (ULO16), 0 },
-/* <mnem> $dr,#$simm8 */
-/* 7 */ { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
-/* <mnem> $dr,$simm8 */
-/* 8 */ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
-/* <mnem> $dr,$sr,#$simm16 */
-/* 9 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
-/* <mnem> $dr,$sr,$simm16 */
-/* 10 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
-/* <mnem> $disp8 */
-/* 11 */ { MNEM, ' ', OP (DISP8), 0 },
-/* <mnem> $disp24 */
-/* 12 */ { MNEM, ' ', OP (DISP24), 0 },
-/* <mnem> $src1,$src2,$disp16 */
-/* 13 */ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
-/* <mnem> $src2,$disp16 */
-/* 14 */ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
-/* <mnem> $src1,$src2 */
-/* 15 */ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
-/* <mnem> $src2,#$simm16 */
-/* 16 */ { MNEM, ' ', OP (SRC2), ',', '#', OP (SIMM16), 0 },
-/* <mnem> $src2,$simm16 */
-/* 17 */ { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
-/* <mnem> $src2,#$uimm16 */
-/* 18 */ { MNEM, ' ', OP (SRC2), ',', '#', OP (UIMM16), 0 },
-/* <mnem> $src2,$uimm16 */
-/* 19 */ { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
-/* <mnem> $src2 */
-/* 20 */ { MNEM, ' ', OP (SRC2), 0 },
-/* <mnem> $sr */
-/* 21 */ { MNEM, ' ', OP (SR), 0 },
-/* <mnem> $dr,@$sr */
-/* 22 */ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
-/* <mnem> $dr,@($sr) */
-/* 23 */ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
-/* <mnem> $dr,@($slo16,$sr) */
-/* 24 */ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
-/* <mnem> $dr,@($sr,$slo16) */
-/* 25 */ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
-/* <mnem> $dr,@$sr+ */
-/* 26 */ { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
-/* <mnem> $dr,#$uimm24 */
-/* 27 */ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM24), 0 },
-/* <mnem> $dr,$uimm24 */
-/* 28 */ { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
-/* <mnem> $dr,$slo16 */
-/* 29 */ { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 },
-/* <mnem> $src1,$src2,$acc */
-/* 30 */ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
-/* <mnem> $dr */
-/* 31 */ { MNEM, ' ', OP (DR), 0 },
-/* <mnem> $dr,$accs */
-/* 32 */ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
-/* <mnem> $dr,$scr */
-/* 33 */ { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
-/* <mnem> $src1 */
-/* 34 */ { MNEM, ' ', OP (SRC1), 0 },
-/* <mnem> $src1,$accs */
-/* 35 */ { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
-/* <mnem> $sr,$dcr */
-/* 36 */ { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
-/* <mnem> */
-/* 37 */ { MNEM, 0 },
-/* <mnem> $accd */
-/* 38 */ { MNEM, ' ', OP (ACCD), 0 },
-/* <mnem> $accd,$accs */
-/* 39 */ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
-/* <mnem> $accd,$accs,#$imm1 */
-/* 40 */ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 },
-/* <mnem> $dr,#$hi16 */
-/* 41 */ { MNEM, ' ', OP (DR), ',', '#', OP (HI16), 0 },
-/* <mnem> $dr,$hi16 */
-/* 42 */ { MNEM, ' ', OP (DR), ',', OP (HI16), 0 },
-/* <mnem> $dr,#$uimm5 */
-/* 43 */ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
-/* <mnem> $dr,$uimm5 */
-/* 44 */ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
-/* <mnem> $src1,@$src2 */
-/* 45 */ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
-/* <mnem> $src1,@($src2) */
-/* 46 */ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
-/* <mnem> $src1,@($slo16,$src2) */
-/* 47 */ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
-/* <mnem> $src1,@($src2,$slo16) */
-/* 48 */ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
-/* <mnem> $src1,@+$src2 */
-/* 49 */ { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
-/* <mnem> $src1,@-$src2 */
-/* 50 */ { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
-/* <mnem> #$uimm4 */
-/* 51 */ { MNEM, ' ', '#', OP (UIMM4), 0 },
-/* <mnem> $uimm4 */
-/* 52 */ { MNEM, ' ', OP (UIMM4), 0 },
-};
-
-#undef MNEM
-#undef OP
-
-static const CGEN_FORMAT format_table[] =
-{
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(dr SI) */
-/* 0 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(slo16 HI)(sr SI)(dr SI) */
-/* 1 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 uimm16)(sr SI)(uimm16 USI)(dr SI) */
-/* 2 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 ulo16)(sr SI)(ulo16 UHI)(dr SI) */
-/* 3 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(dr SI)(simm8 SI)(dr SI) */
-/* 4 */ { 16, 16, 0xf000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(condbit UBI)(dr SI) */
-/* 5 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(condbit UBI)(dr SI) */
-/* 6 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */
-/* 7 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI) */
-/* 8 */ { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8) */
-/* 9 */ { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI) */
-/* 10 */ { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24) */
-/* 11 */ { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI)(pc USI) */
-/* 12 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI)(pc USI) */
-/* 13 */ { 32, 32, 0xfff00000 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
-/* 14 */ { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
-/* 15 */ { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
-/* 16 */ { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
-/* 17 */ { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI) */
-/* 18 */ { 16, 16, 0xff00 },
-/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI) */
-/* 19 */ { 32, 32, 0xff000000 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */
-/* 20 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-simm16 simm16)(simm16 SI)(src2 SI)(condbit UBI) */
-/* 21 */ { 32, 32, 0xfff00000 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-uimm16 uimm16)(src2 SI)(uimm16 USI)(condbit UBI) */
-/* 22 */ { 32, 32, 0xfff00000 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(src2 SI)(condbit UBI) */
-/* 23 */ { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */
-/* 24 */ { 32, 32, 0xf0f0ffff },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI)(pc USI) */
-/* 25 */ { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(pc USI)(h-gr-14 SI) */
-/* 26 */ { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI)(pc USI) */
-/* 27 */ { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */
-/* 28 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr) */
-/* 29 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 SI)(slo16 HI)(sr SI)(dr SI) */
-/* 30 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16) */
-/* 31 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr QI)(sr SI)(dr SI) */
-/* 32 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 QI)(slo16 HI)(sr SI)(dr SI) */
-/* 33 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr HI)(sr SI)(dr SI) */
-/* 34 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 HI)(slo16 HI)(sr SI)(dr SI) */
-/* 35 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(sr SI) */
-/* 36 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-uimm24 uimm24)(uimm24 VM)(dr SI) */
-/* 37 */ { 32, 32, 0xf0000000 },
-/* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(simm8 SI)(dr SI) */
-/* 38 */ { 16, 16, 0xf000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */
-/* 39 */ { 32, 32, 0xf0ff0000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(h-lock-0 UBI) */
-/* 40 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */
-/* 41 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(acc DI)(src1 SI)(src2 SI)(acc DI) */
-/* 42 */ { 16, 16, 0xf070 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(accum DI) */
-/* 43 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(src1 SI)(src2 SI)(acc DI) */
-/* 44 */ { 16, 16, 0xf070 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(sr SI)(dr SI) */
-/* 45 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(accum DI)(dr SI) */
-/* 46 */ { 16, 16, 0xf0ff },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */
-/* 47 */ { 16, 16, 0xf0f3 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr USI)(dr SI) */
-/* 48 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */
-/* 49 */ { 16, 16, 0xf0ff },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */
-/* 50 */ { 16, 16, 0xf0f3 },
-/* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr USI) */
-/* 51 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */
-/* 52 */ { 16, 16, 0xffff },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */
-/* 53 */ { 16, 16, 0xffff },
-/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #) */
-/* 54 */ { 16, 16, 0xf3ff },
-/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #) */
-/* 55 */ { 16, 16, 0xf3f3 },
-/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */
-/* 56 */ { 16, 16, 0xf3f2 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-bcond-0 VM)(h-bie-0 VM)(h-bpc-0 VM)(h-bsm-0 VM)(condbit UBI)(pc USI)(h-ie-0 VM)(h-sm-0 VM) */
-/* 57 */ { 16, 16, 0xffff },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-hi16 hi16)(hi16 UHI)(dr SI) */
-/* 58 */ { 32, 32, 0xf0ff0000 },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(dr SI) */
-/* 59 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 dr)(f-shift-op2 #)(f-uimm5 uimm5)(dr SI)(uimm5 USI)(dr SI) */
-/* 60 */ { 16, 16, 0xf0e0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI) */
-/* 61 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2) */
-/* 62 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 SI) */
-/* 63 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16) */
-/* 64 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 QI) */
-/* 65 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 QI) */
-/* 66 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 HI) */
-/* 67 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 HI) */
-/* 68 */ { 32, 32, 0xf0f00000 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */
-/* 69 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(pc USI)(h-cr-0 SI)(uimm4 USI)(pc USI)(h-cr-0 SI)(h-cr-6 SI) */
-/* 70 */ { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4) */
-/* 71 */ { 16, 16, 0xfff0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-lock-0 UBI)(src1 SI)(src2 SI)(h-memory-src2 SI)(h-lock-0 UBI) */
-/* 72 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */
-/* 73 */ { 16, 16, 0xf0ff },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
-/* 74 */ { 16, 16, 0xf0ff },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(sr SI)(dr SI) */
-/* 75 */ { 32, 32, 0xf0f0ffff },
-/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(condbit UBI)(sr SI)(dr SI) */
-/* 76 */ { 32, 32, 0xf0f0ffff },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
-/* 77 */ { 16, 16, 0xffff },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */
-/* 78 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
-/* 79 */ { 16, 16, 0xf0f0 },
-/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */
-/* 80 */ { 16, 16, 0xffff },
-};
-
-#define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
-#define SYN(n) (& syntax_table[n])
-#define FMT(n) (& format_table[n])
-
/* The instruction table. */
const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
@@ -1210,231 +923,297 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* add $dr,$sr */
{
{ 1, 1, 1, 1 },
- "add", "add", SYN (0), FMT (0), 0xa0,
+ "add", "add",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0xa0,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
/* add3 $dr,$sr,#$slo16 */
{
{ 1, 1, 1, 1 },
- "add3", "add3", SYN (1), FMT (1), 0x80a00000,
+ "add3", "add3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SLO16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80a00000,
& fmt_1_add3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* add3 $dr,$sr,$slo16 */
{
{ 1, 1, 1, 1 },
- "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
+ "add3.a", "add3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SLO16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80a00000,
& fmt_1_add3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* and $dr,$sr */
{
{ 1, 1, 1, 1 },
- "and", "and", SYN (0), FMT (0), 0xc0,
+ "and", "and",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0xc0,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
/* and3 $dr,$sr,#$uimm16 */
{
{ 1, 1, 1, 1 },
- "and3", "and3", SYN (3), FMT (2), 0x80c00000,
+ "and3", "and3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80c00000,
& fmt_2_and3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* and3 $dr,$sr,$uimm16 */
{
{ 1, 1, 1, 1 },
- "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
+ "and3.a", "and3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80c00000,
& fmt_2_and3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* or $dr,$sr */
{
{ 1, 1, 1, 1 },
- "or", "or", SYN (0), FMT (0), 0xe0,
+ "or", "or",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0xe0,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
/* or3 $dr,$sr,#$ulo16 */
{
{ 1, 1, 1, 1 },
- "or3", "or3", SYN (5), FMT (3), 0x80e00000,
+ "or3", "or3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (ULO16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80e00000,
& fmt_3_or3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* or3 $dr,$sr,$ulo16 */
{
{ 1, 1, 1, 1 },
- "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
+ "or3.a", "or3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (ULO16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80e00000,
& fmt_3_or3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* xor $dr,$sr */
{
{ 1, 1, 1, 1 },
- "xor", "xor", SYN (0), FMT (0), 0xd0,
+ "xor", "xor",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0xd0,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
},
/* xor3 $dr,$sr,#$uimm16 */
{
{ 1, 1, 1, 1 },
- "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
+ "xor3", "xor3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80d00000,
& fmt_2_and3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* xor3 $dr,$sr,$uimm16 */
{
{ 1, 1, 1, 1 },
- "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
+ "xor3.a", "xor3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80d00000,
& fmt_2_and3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* addi $dr,#$simm8 */
{
{ 1, 1, 1, 1 },
- "addi", "addi", SYN (7), FMT (4), 0x4000,
+ "addi", "addi",
+ { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
+ { 16, 16, 0xf000 }, 0x4000,
& fmt_4_addi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* addi $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "addi.a", "addi", SYN (8), FMT (4), 0x4000,
+ "addi.a", "addi",
+ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
+ { 16, 16, 0xf000 }, 0x4000,
& fmt_4_addi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
},
/* addv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "addv", "addv", SYN (0), FMT (5), 0x80,
+ "addv", "addv",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x80,
& fmt_5_addv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* addv3 $dr,$sr,#$simm16 */
{
{ 1, 1, 1, 1 },
- "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
+ "addv3", "addv3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80800000,
& fmt_6_addv3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* addv3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
+ "addv3.a", "addv3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x80800000,
& fmt_6_addv3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* addx $dr,$sr */
{
{ 1, 1, 1, 1 },
- "addx", "addx", SYN (0), FMT (7), 0x90,
+ "addx", "addx",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x90,
& fmt_7_addx_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* bc $disp8 */
{
{ 1, 1, 1, 1 },
- "bc8", "bc", SYN (11), FMT (8), 0x7c00,
+ "bc8", "bc",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7c00,
& fmt_8_bc8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bc.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
+ "bc8.s", "bc.s",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7c00,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bc $disp24 */
{
{ 1, 1, 1, 1 },
- "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
+ "bc24", "bc",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xfc000000,
& fmt_10_bc24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bc.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
+ "bc24.l", "bc.l",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xfc000000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* beq $src1,$src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "beq", "beq", SYN (13), FMT (12), 0xb0000000,
+ "beq", "beq",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xf0f00000 }, 0xb0000000,
& fmt_12_beq_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* beqz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
+ "beqz", "beqz",
+ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xfff00000 }, 0xb0800000,
& fmt_13_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bgez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
+ "bgez", "bgez",
+ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xfff00000 }, 0xb0b00000,
& fmt_13_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bgtz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
+ "bgtz", "bgtz",
+ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xfff00000 }, 0xb0d00000,
& fmt_13_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* blez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
+ "blez", "blez",
+ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xfff00000 }, 0xb0c00000,
& fmt_13_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bltz $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
+ "bltz", "bltz",
+ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xfff00000 }, 0xb0a00000,
& fmt_13_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bnez $src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
+ "bnez", "bnez",
+ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xfff00000 }, 0xb0900000,
& fmt_13_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bl $disp8 */
{
{ 1, 1, 1, 1 },
- "bl8", "bl", SYN (11), FMT (14), 0x7e00,
+ "bl8", "bl",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7e00,
& fmt_14_bl8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
+ "bl8.s", "bl.s",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7e00,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bl $disp24 */
{
{ 1, 1, 1, 1 },
- "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
+ "bl24", "bl",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xfe000000,
& fmt_15_bl24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
+ "bl24.l", "bl.l",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xfe000000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -1442,7 +1221,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bcl $disp8 */
{
{ 1, 1, 1, 1 },
- "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
+ "bcl8", "bcl",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7800,
& fmt_16_bcl8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
@@ -1451,7 +1232,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bcl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
+ "bcl8.s", "bcl.s",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7800,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
@@ -1460,7 +1243,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bcl $disp24 */
{
{ 1, 1, 1, 1 },
- "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
+ "bcl24", "bcl",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xf8000000,
& fmt_17_bcl24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -1469,7 +1254,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bcl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
+ "bcl24.l", "bcl.l",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xf8000000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -1477,63 +1264,81 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bnc $disp8 */
{
{ 1, 1, 1, 1 },
- "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
+ "bnc8", "bnc",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7d00,
& fmt_8_bc8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bnc.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
+ "bnc8.s", "bnc.s",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7d00,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bnc $disp24 */
{
{ 1, 1, 1, 1 },
- "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
+ "bnc24", "bnc",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xfd000000,
& fmt_10_bc24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bnc.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
+ "bnc24.l", "bnc.l",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xfd000000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bne $src1,$src2,$disp16 */
{
{ 1, 1, 1, 1 },
- "bne", "bne", SYN (13), FMT (12), 0xb0100000,
+ "bne", "bne",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
+ { 32, 32, 0xf0f00000 }, 0xb0100000,
& fmt_12_beq_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bra $disp8 */
{
{ 1, 1, 1, 1 },
- "bra8", "bra", SYN (11), FMT (18), 0x7f00,
+ "bra8", "bra",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7f00,
& fmt_18_bra8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bra.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
+ "bra8.s", "bra.s",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7f00,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* bra $disp24 */
{
{ 1, 1, 1, 1 },
- "bra24", "bra", SYN (12), FMT (19), 0xff000000,
+ "bra24", "bra",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xff000000,
& fmt_19_bra24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
/* bra.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
+ "bra24.l", "bra.l",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xff000000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -1541,7 +1346,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bncl $disp8 */
{
{ 1, 1, 1, 1 },
- "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
+ "bncl8", "bncl",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7900,
& fmt_16_bcl8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
@@ -1550,7 +1357,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bncl.s $disp8 */
{
{ 1, 1, 1, 1 },
- "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
+ "bncl8.s", "bncl.s",
+ { MNEM, ' ', OP (DISP8), 0 },
+ { 16, 16, 0xff00 }, 0x7900,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
@@ -1559,7 +1368,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bncl $disp24 */
{
{ 1, 1, 1, 1 },
- "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
+ "bncl24", "bncl",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xf9000000,
& fmt_17_bcl24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -1568,7 +1379,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* bncl.l $disp24 */
{
{ 1, 1, 1, 1 },
- "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
+ "bncl24.l", "bncl.l",
+ { MNEM, ' ', OP (DISP24), 0 },
+ { 32, 32, 0xff000000 }, 0xf9000000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -1576,42 +1389,54 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* cmp $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmp", "cmp", SYN (15), FMT (20), 0x40,
+ "cmp", "cmp",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x40,
& fmt_20_cmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* cmpi $src2,#$simm16 */
{
{ 1, 1, 1, 1 },
- "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
+ "cmpi", "cmpi",
+ { MNEM, ' ', OP (SRC2), ',', '#', OP (SIMM16), 0 },
+ { 32, 32, 0xfff00000 }, 0x80400000,
& fmt_21_cmpi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* cmpi $src2,$simm16 */
{
{ 1, 1, 1, 1 },
- "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
+ "cmpi.a", "cmpi",
+ { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
+ { 32, 32, 0xfff00000 }, 0x80400000,
& fmt_21_cmpi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* cmpu $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
+ "cmpu", "cmpu",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x50,
& fmt_20_cmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* cmpui $src2,#$uimm16 */
{
{ 1, 1, 1, 1 },
- "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
+ "cmpui", "cmpui",
+ { MNEM, ' ', OP (SRC2), ',', '#', OP (UIMM16), 0 },
+ { 32, 32, 0xfff00000 }, 0x80500000,
& fmt_22_cmpui_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* cmpui $src2,$uimm16 */
{
{ 1, 1, 1, 1 },
- "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
+ "cmpui.a", "cmpui",
+ { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
+ { 32, 32, 0xfff00000 }, 0x80500000,
& fmt_22_cmpui_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -1619,7 +1444,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* cmpeq $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
+ "cmpeq", "cmpeq",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x60,
& fmt_20_cmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
@@ -1628,7 +1455,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* cmpz $src2 */
{
{ 1, 1, 1, 1 },
- "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
+ "cmpz", "cmpz",
+ { MNEM, ' ', OP (SRC2), 0 },
+ { 16, 16, 0xfff0 }, 0x70,
& fmt_23_cmpz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
@@ -1636,28 +1465,36 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* div $dr,$sr */
{
{ 1, 1, 1, 1 },
- "div", "div", SYN (0), FMT (24), 0x90000000,
+ "div", "div",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x90000000,
& fmt_24_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* divu $dr,$sr */
{
{ 1, 1, 1, 1 },
- "divu", "divu", SYN (0), FMT (24), 0x90100000,
+ "divu", "divu",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x90100000,
& fmt_24_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* rem $dr,$sr */
{
{ 1, 1, 1, 1 },
- "rem", "rem", SYN (0), FMT (24), 0x90200000,
+ "rem", "rem",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x90200000,
& fmt_24_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* remu $dr,$sr */
{
{ 1, 1, 1, 1 },
- "remu", "remu", SYN (0), FMT (24), 0x90300000,
+ "remu", "remu",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x90300000,
& fmt_24_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -1665,7 +1502,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* divh $dr,$sr */
{
{ 1, 1, 1, 1 },
- "divh", "divh", SYN (0), FMT (24), 0x90000010,
+ "divh", "divh",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x90000010,
& fmt_24_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -1674,7 +1513,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* jc $sr */
{
{ 1, 1, 1, 1 },
- "jc", "jc", SYN (21), FMT (25), 0x1cc0,
+ "jc", "jc",
+ { MNEM, ' ', OP (SR), 0 },
+ { 16, 16, 0xfff0 }, 0x1cc0,
& fmt_25_jc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
@@ -1683,7 +1524,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* jnc $sr */
{
{ 1, 1, 1, 1 },
- "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
+ "jnc", "jnc",
+ { MNEM, ' ', OP (SR), 0 },
+ { 16, 16, 0xfff0 }, 0x1dc0,
& fmt_25_jc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
@@ -1691,231 +1534,297 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* jl $sr */
{
{ 1, 1, 1, 1 },
- "jl", "jl", SYN (21), FMT (26), 0x1ec0,
+ "jl", "jl",
+ { MNEM, ' ', OP (SR), 0 },
+ { 16, 16, 0xfff0 }, 0x1ec0,
& fmt_26_jl_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* jmp $sr */
{
{ 1, 1, 1, 1 },
- "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
+ "jmp", "jmp",
+ { MNEM, ' ', OP (SR), 0 },
+ { 16, 16, 0xfff0 }, 0x1fc0,
& fmt_27_jmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* ld $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ld", "ld", SYN (22), FMT (28), 0x20c0,
+ "ld", "ld",
+ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x20c0,
& fmt_28_ld_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* ld $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
+ "ld-2", "ld",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x20c0,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* ld $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
+ "ld-d", "ld",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0c00000,
& fmt_30_ld_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* ld $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
+ "ld-d2", "ld",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0c00000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldb $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldb", "ldb", SYN (22), FMT (32), 0x2080,
+ "ldb", "ldb",
+ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x2080,
& fmt_32_ldb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* ldb $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
+ "ldb-2", "ldb",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x2080,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* ldb $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
+ "ldb-d", "ldb",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0800000,
& fmt_33_ldb_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldb $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
+ "ldb-d2", "ldb",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0800000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldh $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
+ "ldh", "ldh",
+ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x20a0,
& fmt_34_ldh_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* ldh $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
+ "ldh-2", "ldh",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x20a0,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* ldh $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
+ "ldh-d", "ldh",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0a00000,
& fmt_35_ldh_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldh $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
+ "ldh-d2", "ldh",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0a00000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldub $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "ldub", "ldub", SYN (22), FMT (32), 0x2090,
+ "ldub", "ldub",
+ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x2090,
& fmt_32_ldb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* ldub $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
+ "ldub-2", "ldub",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x2090,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* ldub $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
+ "ldub-d", "ldub",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0900000,
& fmt_33_ldb_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldub $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
+ "ldub-d2", "ldub",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0900000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* lduh $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
+ "lduh", "lduh",
+ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x20b0,
& fmt_34_ldh_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* lduh $dr,@($sr) */
{
{ 1, 1, 1, 1 },
- "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
+ "lduh-2", "lduh",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x20b0,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* lduh $dr,@($slo16,$sr) */
{
{ 1, 1, 1, 1 },
- "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
+ "lduh-d", "lduh",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0b00000,
& fmt_35_ldh_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* lduh $dr,@($sr,$slo16) */
{
{ 1, 1, 1, 1 },
- "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
+ "lduh-d2", "lduh",
+ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0b00000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* ld $dr,@$sr+ */
{
{ 1, 1, 1, 1 },
- "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
+ "ld-plus", "ld",
+ { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
+ { 16, 16, 0xf0f0 }, 0x20e0,
& fmt_36_ld_plus_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* ld24 $dr,#$uimm24 */
{
{ 1, 1, 1, 1 },
- "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
+ "ld24", "ld24",
+ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM24), 0 },
+ { 32, 32, 0xf0000000 }, 0xe0000000,
& fmt_37_ld24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* ld24 $dr,$uimm24 */
{
{ 1, 1, 1, 1 },
- "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
+ "ld24.a", "ld24",
+ { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
+ { 32, 32, 0xf0000000 }, 0xe0000000,
& fmt_37_ld24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldi $dr,#$simm8 */
{
{ 1, 1, 1, 1 },
- "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
+ "ldi8", "ldi",
+ { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
+ { 16, 16, 0xf000 }, 0x6000,
& fmt_38_ldi8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* ldi $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
+ "ldi8.a", "ldi",
+ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
+ { 16, 16, 0xf000 }, 0x6000,
& fmt_38_ldi8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
},
/* ldi8 $dr,#$simm8 */
{
{ 1, 1, 1, 1 },
- "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
+ "ldi8a", "ldi8",
+ { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 },
+ { 16, 16, 0xf000 }, 0x6000,
& fmt_38_ldi8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
},
/* ldi8 $dr,$simm8 */
{
{ 1, 1, 1, 1 },
- "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
+ "ldi8a.a", "ldi8",
+ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
+ { 16, 16, 0xf000 }, 0x6000,
& fmt_38_ldi8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
},
/* ldi $dr,$slo16 */
{
{ 1, 1, 1, 1 },
- "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
+ "ldi16", "ldi",
+ { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 },
+ { 32, 32, 0xf0ff0000 }, 0x90f00000,
& fmt_39_ldi16_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* ldi16 $dr,$slo16 */
{
{ 1, 1, 1, 1 },
- "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
+ "ldi16a", "ldi16",
+ { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 },
+ { 32, 32, 0xf0ff0000 }, 0x90f00000,
& fmt_39_ldi16_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* lock $dr,@$sr */
{
{ 1, 1, 1, 1 },
- "lock", "lock", SYN (22), FMT (40), 0x20d0,
+ "lock", "lock",
+ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x20d0,
& fmt_40_lock_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* machi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "machi", "machi", SYN (15), FMT (41), 0x3040,
+ "machi", "machi",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3040,
& fmt_41_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -1923,7 +1832,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* machi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "machi-a", "machi", SYN (30), FMT (42), 0x3040,
+ "machi-a", "machi",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+ { 16, 16, 0xf070 }, 0x3040,
& fmt_42_machi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -1931,7 +1842,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* maclo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "maclo", "maclo", SYN (15), FMT (41), 0x3050,
+ "maclo", "maclo",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3050,
& fmt_41_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -1939,7 +1852,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* maclo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
+ "maclo-a", "maclo",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+ { 16, 16, 0xf070 }, 0x3050,
& fmt_42_machi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -1947,28 +1862,36 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* macwhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
+ "macwhi", "macwhi",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3060,
& fmt_41_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* macwlo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
+ "macwlo", "macwlo",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3070,
& fmt_41_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mul $dr,$sr */
{
{ 1, 1, 1, 1 },
- "mul", "mul", SYN (0), FMT (0), 0x1060,
+ "mul", "mul",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x1060,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mulhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
+ "mulhi", "mulhi",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3000,
& fmt_43_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -1976,7 +1899,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mulhi $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
+ "mulhi-a", "mulhi",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+ { 16, 16, 0xf070 }, 0x3000,
& fmt_44_mulhi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -1984,7 +1909,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mullo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mullo", "mullo", SYN (15), FMT (43), 0x3010,
+ "mullo", "mullo",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3010,
& fmt_43_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -1992,7 +1919,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mullo $src1,$src2,$acc */
{
{ 1, 1, 1, 1 },
- "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
+ "mullo-a", "mullo",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
+ { 16, 16, 0xf070 }, 0x3010,
& fmt_44_mulhi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2000,28 +1929,36 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mulwhi $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
+ "mulwhi", "mulwhi",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3020,
& fmt_43_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mulwlo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
+ "mulwlo", "mulwlo",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x3030,
& fmt_43_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "mv", "mv", SYN (0), FMT (45), 0x1080,
+ "mv", "mv",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x1080,
& fmt_45_mv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* mvfachi $dr */
{
{ 1, 1, 1, 1 },
- "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
+ "mvfachi", "mvfachi",
+ { MNEM, ' ', OP (DR), 0 },
+ { 16, 16, 0xf0ff }, 0x50f0,
& fmt_46_mvfachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -2029,7 +1966,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvfachi $dr,$accs */
{
{ 1, 1, 1, 1 },
- "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
+ "mvfachi-a", "mvfachi",
+ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
+ { 16, 16, 0xf0f3 }, 0x50f0,
& fmt_47_mvfachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2037,7 +1976,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvfaclo $dr */
{
{ 1, 1, 1, 1 },
- "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
+ "mvfaclo", "mvfaclo",
+ { MNEM, ' ', OP (DR), 0 },
+ { 16, 16, 0xf0ff }, 0x50f1,
& fmt_46_mvfachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -2045,7 +1986,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvfaclo $dr,$accs */
{
{ 1, 1, 1, 1 },
- "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
+ "mvfaclo-a", "mvfaclo",
+ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
+ { 16, 16, 0xf0f3 }, 0x50f1,
& fmt_47_mvfachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2053,7 +1996,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvfacmi $dr */
{
{ 1, 1, 1, 1 },
- "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
+ "mvfacmi", "mvfacmi",
+ { MNEM, ' ', OP (DR), 0 },
+ { 16, 16, 0xf0ff }, 0x50f2,
& fmt_46_mvfachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -2061,7 +2006,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvfacmi $dr,$accs */
{
{ 1, 1, 1, 1 },
- "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
+ "mvfacmi-a", "mvfacmi",
+ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
+ { 16, 16, 0xf0f3 }, 0x50f2,
& fmt_47_mvfachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2069,14 +2016,18 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvfc $dr,$scr */
{
{ 1, 1, 1, 1 },
- "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
+ "mvfc", "mvfc",
+ { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
+ { 16, 16, 0xf0f0 }, 0x1090,
& fmt_48_mvfc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* mvtachi $src1 */
{
{ 1, 1, 1, 1 },
- "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
+ "mvtachi", "mvtachi",
+ { MNEM, ' ', OP (SRC1), 0 },
+ { 16, 16, 0xf0ff }, 0x5070,
& fmt_49_mvtachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -2084,7 +2035,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvtachi $src1,$accs */
{
{ 1, 1, 1, 1 },
- "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
+ "mvtachi-a", "mvtachi",
+ { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
+ { 16, 16, 0xf0f3 }, 0x5070,
& fmt_50_mvtachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2092,7 +2045,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvtaclo $src1 */
{
{ 1, 1, 1, 1 },
- "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
+ "mvtaclo", "mvtaclo",
+ { MNEM, ' ', OP (SRC1), 0 },
+ { 16, 16, 0xf0ff }, 0x5071,
& fmt_49_mvtachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -2100,7 +2055,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvtaclo $src1,$accs */
{
{ 1, 1, 1, 1 },
- "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
+ "mvtaclo-a", "mvtaclo",
+ { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
+ { 16, 16, 0xf0f3 }, 0x5071,
& fmt_50_mvtachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2108,35 +2065,45 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mvtc $sr,$dcr */
{
{ 1, 1, 1, 1 },
- "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
+ "mvtc", "mvtc",
+ { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
+ { 16, 16, 0xf0f0 }, 0x10a0,
& fmt_51_mvtc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* neg $dr,$sr */
{
{ 1, 1, 1, 1 },
- "neg", "neg", SYN (0), FMT (45), 0x30,
+ "neg", "neg",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x30,
& fmt_45_mv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* nop */
{
{ 1, 1, 1, 1 },
- "nop", "nop", SYN (37), FMT (52), 0x7000,
+ "nop", "nop",
+ { MNEM, 0 },
+ { 16, 16, 0xffff }, 0x7000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* not $dr,$sr */
{
{ 1, 1, 1, 1 },
- "not", "not", SYN (0), FMT (45), 0xb0,
+ "not", "not",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0xb0,
& fmt_45_mv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* rac */
{
{ 1, 1, 1, 1 },
- "rac", "rac", SYN (37), FMT (53), 0x5090,
+ "rac", "rac",
+ { MNEM, 0 },
+ { 16, 16, 0xffff }, 0x5090,
& fmt_53_rac_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -2144,7 +2111,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rac $accd */
{
{ 1, 1, 1, 1 },
- "rac-d", "rac", SYN (38), FMT (54), 0x5090,
+ "rac-d", "rac",
+ { MNEM, ' ', OP (ACCD), 0 },
+ { 16, 16, 0xf3ff }, 0x5090,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -2153,7 +2122,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rac $accd,$accs */
{
{ 1, 1, 1, 1 },
- "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
+ "rac-ds", "rac",
+ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
+ { 16, 16, 0xf3f3 }, 0x5090,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -2162,7 +2133,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rac $accd,$accs,#$imm1 */
{
{ 1, 1, 1, 1 },
- "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
+ "rac-dsi", "rac",
+ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 },
+ { 16, 16, 0xf3f2 }, 0x5090,
& fmt_56_rac_dsi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2170,7 +2143,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rach */
{
{ 1, 1, 1, 1 },
- "rach", "rach", SYN (37), FMT (53), 0x5080,
+ "rach", "rach",
+ { MNEM, 0 },
+ { 16, 16, 0xffff }, 0x5080,
& fmt_53_rac_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
@@ -2178,7 +2153,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rach $accd */
{
{ 1, 1, 1, 1 },
- "rach-d", "rach", SYN (38), FMT (54), 0x5080,
+ "rach-d", "rach",
+ { MNEM, ' ', OP (ACCD), 0 },
+ { 16, 16, 0xf3ff }, 0x5080,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -2187,7 +2164,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rach $accd,$accs */
{
{ 1, 1, 1, 1 },
- "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
+ "rach-ds", "rach",
+ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
+ { 16, 16, 0xf3f3 }, 0x5080,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -2196,7 +2175,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rach $accd,$accs,#$imm1 */
{
{ 1, 1, 1, 1 },
- "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
+ "rach-dsi", "rach",
+ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 },
+ { 16, 16, 0xf3f2 }, 0x5080,
& fmt_56_rac_dsi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2204,280 +2185,360 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* rte */
{
{ 1, 1, 1, 1 },
- "rte", "rte", SYN (37), FMT (57), 0x10d6,
+ "rte", "rte",
+ { MNEM, 0 },
+ { 16, 16, 0xffff }, 0x10d6,
& fmt_57_rte_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* seth $dr,#$hi16 */
{
{ 1, 1, 1, 1 },
- "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
+ "seth", "seth",
+ { MNEM, ' ', OP (DR), ',', '#', OP (HI16), 0 },
+ { 32, 32, 0xf0ff0000 }, 0xd0c00000,
& fmt_58_seth_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* seth $dr,$hi16 */
{
{ 1, 1, 1, 1 },
- "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
+ "seth.a", "seth",
+ { MNEM, ' ', OP (DR), ',', OP (HI16), 0 },
+ { 32, 32, 0xf0ff0000 }, 0xd0c00000,
& fmt_58_seth_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* sll $dr,$sr */
{
{ 1, 1, 1, 1 },
- "sll", "sll", SYN (0), FMT (0), 0x1040,
+ "sll", "sll",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x1040,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* sll3 $dr,$sr,#$simm16 */
{
{ 1, 1, 1, 1 },
- "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
+ "sll3", "sll3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x90c00000,
& fmt_59_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* sll3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
+ "sll3.a", "sll3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x90c00000,
& fmt_59_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* slli $dr,#$uimm5 */
{
{ 1, 1, 1, 1 },
- "slli", "slli", SYN (43), FMT (60), 0x5040,
+ "slli", "slli",
+ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
+ { 16, 16, 0xf0e0 }, 0x5040,
& fmt_60_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* slli $dr,$uimm5 */
{
{ 1, 1, 1, 1 },
- "slli.a", "slli", SYN (44), FMT (60), 0x5040,
+ "slli.a", "slli",
+ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
+ { 16, 16, 0xf0e0 }, 0x5040,
& fmt_60_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* sra $dr,$sr */
{
{ 1, 1, 1, 1 },
- "sra", "sra", SYN (0), FMT (0), 0x1020,
+ "sra", "sra",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x1020,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* sra3 $dr,$sr,#$simm16 */
{
{ 1, 1, 1, 1 },
- "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
+ "sra3", "sra3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x90a00000,
& fmt_59_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* sra3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
+ "sra3.a", "sra3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x90a00000,
& fmt_59_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* srai $dr,#$uimm5 */
{
{ 1, 1, 1, 1 },
- "srai", "srai", SYN (43), FMT (60), 0x5020,
+ "srai", "srai",
+ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
+ { 16, 16, 0xf0e0 }, 0x5020,
& fmt_60_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* srai $dr,$uimm5 */
{
{ 1, 1, 1, 1 },
- "srai.a", "srai", SYN (44), FMT (60), 0x5020,
+ "srai.a", "srai",
+ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
+ { 16, 16, 0xf0e0 }, 0x5020,
& fmt_60_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* srl $dr,$sr */
{
{ 1, 1, 1, 1 },
- "srl", "srl", SYN (0), FMT (0), 0x1000,
+ "srl", "srl",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x1000,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* srl3 $dr,$sr,#$simm16 */
{
{ 1, 1, 1, 1 },
- "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
+ "srl3", "srl3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x90800000,
& fmt_59_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* srl3 $dr,$sr,$simm16 */
{
{ 1, 1, 1, 1 },
- "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
+ "srl3.a", "srl3",
+ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
+ { 32, 32, 0xf0f00000 }, 0x90800000,
& fmt_59_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* srli $dr,#$uimm5 */
{
{ 1, 1, 1, 1 },
- "srli", "srli", SYN (43), FMT (60), 0x5000,
+ "srli", "srli",
+ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 },
+ { 16, 16, 0xf0e0 }, 0x5000,
& fmt_60_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* srli $dr,$uimm5 */
{
{ 1, 1, 1, 1 },
- "srli.a", "srli", SYN (44), FMT (60), 0x5000,
+ "srli.a", "srli",
+ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
+ { 16, 16, 0xf0e0 }, 0x5000,
& fmt_60_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* st $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "st", "st", SYN (45), FMT (61), 0x2040,
+ "st", "st",
+ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x2040,
& fmt_61_st_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* st $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "st-2", "st", SYN (46), FMT (62), 0x2040,
+ "st-2", "st",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x2040,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* st $src1,@($slo16,$src2) */
{
{ 1, 1, 1, 1 },
- "st-d", "st", SYN (47), FMT (63), 0xa0400000,
+ "st-d", "st",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0400000,
& fmt_63_st_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* st $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
+ "st-d2", "st",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0400000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* stb $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "stb", "stb", SYN (45), FMT (65), 0x2000,
+ "stb", "stb",
+ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x2000,
& fmt_65_stb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* stb $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "stb-2", "stb", SYN (46), FMT (62), 0x2000,
+ "stb-2", "stb",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x2000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* stb $src1,@($slo16,$src2) */
{
{ 1, 1, 1, 1 },
- "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
+ "stb-d", "stb",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0000000,
& fmt_66_stb_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* stb $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
+ "stb-d2", "stb",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0000000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* sth $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "sth", "sth", SYN (45), FMT (67), 0x2020,
+ "sth", "sth",
+ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x2020,
& fmt_67_sth_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* sth $src1,@($src2) */
{
{ 1, 1, 1, 1 },
- "sth-2", "sth", SYN (46), FMT (62), 0x2020,
+ "sth-2", "sth",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
+ { 16, 16, 0xf0f0 }, 0x2020,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
},
/* sth $src1,@($slo16,$src2) */
{
{ 1, 1, 1, 1 },
- "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
+ "sth-d", "sth",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0200000,
& fmt_68_sth_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
},
/* sth $src1,@($src2,$slo16) */
{
{ 1, 1, 1, 1 },
- "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
+ "sth-d2", "sth",
+ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
+ { 32, 32, 0xf0f00000 }, 0xa0200000,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* st $src1,@+$src2 */
{
{ 1, 1, 1, 1 },
- "st-plus", "st", SYN (49), FMT (69), 0x2060,
+ "st-plus", "st",
+ { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x2060,
& fmt_69_st_plus_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* st $src1,@-$src2 */
{
{ 1, 1, 1, 1 },
- "st-minus", "st", SYN (50), FMT (69), 0x2070,
+ "st-minus", "st",
+ { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x2070,
& fmt_69_st_plus_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* sub $dr,$sr */
{
{ 1, 1, 1, 1 },
- "sub", "sub", SYN (0), FMT (0), 0x20,
+ "sub", "sub",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x20,
& fmt_0_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* subv $dr,$sr */
{
{ 1, 1, 1, 1 },
- "subv", "subv", SYN (0), FMT (5), 0x0,
+ "subv", "subv",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x0,
& fmt_5_addv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* subx $dr,$sr */
{
{ 1, 1, 1, 1 },
- "subx", "subx", SYN (0), FMT (7), 0x10,
+ "subx", "subx",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 16, 16, 0xf0f0 }, 0x10,
& fmt_7_addx_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
},
/* trap #$uimm4 */
{
{ 1, 1, 1, 1 },
- "trap", "trap", SYN (51), FMT (70), 0x10f0,
+ "trap", "trap",
+ { MNEM, ' ', '#', OP (UIMM4), 0 },
+ { 16, 16, 0xfff0 }, 0x10f0,
& fmt_70_trap_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* trap $uimm4 */
{
{ 1, 1, 1, 1 },
- "trap.a", "trap", SYN (52), FMT (71), 0x10f0,
+ "trap.a", "trap",
+ { MNEM, ' ', OP (UIMM4), 0 },
+ { 16, 16, 0xfff0 }, 0x10f0,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
},
/* unlock $src1,@$src2 */
{
{ 1, 1, 1, 1 },
- "unlock", "unlock", SYN (45), FMT (72), 0x2050,
+ "unlock", "unlock",
+ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x2050,
& fmt_72_unlock_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
},
/* push $src1 */
{
{ 1, 1, 1, 1 },
- "push", "push", SYN (34), FMT (73), 0x207f,
+ "push", "push",
+ { MNEM, ' ', OP (SRC1), 0 },
+ { 16, 16, 0xf0ff }, 0x207f,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
/* pop $dr */
{
{ 1, 1, 1, 1 },
- "pop", "pop", SYN (31), FMT (74), 0x20ef,
+ "pop", "pop",
+ { MNEM, ' ', OP (DR), 0 },
+ { 16, 16, 0xf0ff }, 0x20ef,
0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
},
@@ -2485,7 +2546,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* satb $dr,$sr */
{
{ 1, 1, 1, 1 },
- "satb", "satb", SYN (0), FMT (75), 0x80000100,
+ "satb", "satb",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x80000100,
& fmt_75_satb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -2494,7 +2557,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* sath $dr,$sr */
{
{ 1, 1, 1, 1 },
- "sath", "sath", SYN (0), FMT (75), 0x80000200,
+ "sath", "sath",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x80000200,
& fmt_75_satb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -2503,7 +2568,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* sat $dr,$sr */
{
{ 1, 1, 1, 1 },
- "sat", "sat", SYN (0), FMT (76), 0x80000000,
+ "sat", "sat",
+ { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
+ { 32, 32, 0xf0f0ffff }, 0x80000000,
& fmt_76_sat_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
@@ -2512,7 +2579,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* pcmpbz $src2 */
{
{ 1, 1, 1, 1 },
- "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
+ "pcmpbz", "pcmpbz",
+ { MNEM, ' ', OP (SRC2), 0 },
+ { 16, 16, 0xfff0 }, 0x370,
& fmt_23_cmpz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
@@ -2521,7 +2590,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* sadd */
{
{ 1, 1, 1, 1 },
- "sadd", "sadd", SYN (37), FMT (77), 0x50e4,
+ "sadd", "sadd",
+ { MNEM, 0 },
+ { 16, 16, 0xffff }, 0x50e4,
& fmt_77_sadd_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2530,7 +2601,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* macwu1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "macwu1", "macwu1", SYN (15), FMT (78), 0x50b0,
+ "macwu1", "macwu1",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x50b0,
& fmt_78_macwu1_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2539,7 +2612,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* msblo $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
+ "msblo", "msblo",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x50d0,
& fmt_41_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2548,7 +2623,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* mulwu1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "mulwu1", "mulwu1", SYN (15), FMT (79), 0x50a0,
+ "mulwu1", "mulwu1",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x50a0,
& fmt_79_mulwu1_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2557,7 +2634,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* maclh1 $src1,$src2 */
{
{ 1, 1, 1, 1 },
- "maclh1", "maclh1", SYN (15), FMT (78), 0x50c0,
+ "maclh1", "maclh1",
+ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
+ { 16, 16, 0xf0f0 }, 0x50c0,
& fmt_78_macwu1_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
@@ -2566,7 +2645,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* sc */
{
{ 1, 1, 1, 1 },
- "sc", "sc", SYN (37), FMT (80), 0x7401,
+ "sc", "sc",
+ { MNEM, 0 },
+ { 16, 16, 0xffff }, 0x7401,
& fmt_80_sc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
},
@@ -2575,7 +2656,9 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
/* snc */
{
{ 1, 1, 1, 1 },
- "snc", "snc", SYN (37), FMT (80), 0x7501,
+ "snc", "snc",
+ { MNEM, 0 },
+ { 16, 16, 0xffff }, 0x7501,
& fmt_80_sc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
},
@@ -2583,8 +2666,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
};
#undef A
-#undef SYN
-#undef FMT
+#undef MNEM
+#undef OP
CGEN_INSN_TABLE m32r_cgen_insn_table =
{
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 09ad058..3fd2f52 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -28,7 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define CGEN_ARCH m32r
/* Given symbol S, return m32r_cgen_<s>. */
-#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s)
+#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
/* Selected cpu families. */
#define HAVE_CPU_M32R
@@ -89,11 +89,7 @@ typedef enum cgen_operand_type {
/* end-sanitize-m32rx */
, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
- , M32R_OPERAND_ACCUM
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ABORT_PARALLEL_EXECUTION
-/* end-sanitize-m32rx */
- , M32R_OPERAND_MAX
+ , M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Non-boolean attributes. */
generated by cgit v1.1 at 2024-12-16 03:46:24 +0000