diff options
| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-23 16:49:42 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-23 19:33:45 +0000 |
| commit | 0674ee5dada21c8deec690ca66d5b2870f13ea49 (patch) | |
| tree | 2db467165d33ec3a9d2fb87e5caa63f292513171 | |
| parent | b2805ed55456cea2694d31fc8627cca17120267b (diff) | |
| download | gdb-0674ee5dada21c8deec690ca66d5b2870f13ea49.zip gdb-0674ee5dada21c8deec690ca66d5b2870f13ea49.tar.gz gdb-0674ee5dada21c8deec690ca66d5b2870f13ea49.tar.bz2 | |
MIPS16: Handle non-extensible instructions correctly
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
34 files changed, 2202 insertions, 111 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 3e45f64..f378262 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,10 @@ +2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + + * testsuite/binutils-all/mips/mips16-extend-insn.d: New test. + * testsuite/binutils-all/mips/mips16-extend-insn.s: New test + source. + * testsuite/binutils-all/mips/mips.exp: Run the new tests. + 2016-12-23 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. diff --git a/binutils/testsuite/binutils-all/mips/mips.exp b/binutils/testsuite/binutils-all/mips/mips.exp index 143fbc4..8393fc0 100644 --- a/binutils/testsuite/binutils-all/mips/mips.exp +++ b/binutils/testsuite/binutils-all/mips/mips.exp @@ -29,4 +29,5 @@ if [is_elf_format] { run_dump_test "mips16-undecoded" run_dump_test "mips16-pcrel" run_dump_test "mips16-extend-noinsn" + run_dump_test "mips16-extend-insn" } diff --git a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d new file mode 100644 index 0000000..fc170c6 --- /dev/null +++ b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d @@ -0,0 +1,335 @@ +#PROG: objcopy +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS16 extensible and non-extensible instruction disassembly +#as: -32 -mips64 + +# Verify interpreted and separate respectively EXTEND prefix disassembly +# for extensible and non-extensible instructions. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> f123 0000 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 0020 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 0040 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 0060 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 0080 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 00a0 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 00c0 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 00e0 addiu s0,sp,6432 +[0-9a-f]+ <[^>]*> f123 0800 la s0,00001940 <foo\+0x1940> +[0-9a-f]+ <[^>]*> f123 0820 la s0,00001944 <foo\+0x1944> +[0-9a-f]+ <[^>]*> f123 0840 la s0,00001948 <foo\+0x1948> +[0-9a-f]+ <[^>]*> f123 0860 la s0,0000194c <foo\+0x194c> +[0-9a-f]+ <[^>]*> f123 0880 la s0,00001950 <foo\+0x1950> +[0-9a-f]+ <[^>]*> f123 08a0 la s0,00001954 <foo\+0x1954> +[0-9a-f]+ <[^>]*> f123 08c0 la s0,00001958 <foo\+0x1958> +[0-9a-f]+ <[^>]*> f123 08e0 la s0,0000195c <foo\+0x195c> +[0-9a-f]+ <[^>]*> f123 1000 b 00003284 <foo\+0x3284> +[0-9a-f]+ <[^>]*> f123 1020 b 00003288 <foo\+0x3288> +[0-9a-f]+ <[^>]*> f123 1040 b 0000328c <foo\+0x328c> +[0-9a-f]+ <[^>]*> f123 1060 b 00003290 <foo\+0x3290> +[0-9a-f]+ <[^>]*> f123 1080 b 00003294 <foo\+0x3294> +[0-9a-f]+ <[^>]*> f123 10a0 b 00003298 <foo\+0x3298> +[0-9a-f]+ <[^>]*> f123 10c0 b 0000329c <foo\+0x329c> +[0-9a-f]+ <[^>]*> f123 10e0 b 000032a0 <foo\+0x32a0> +[0-9a-f]+ <[^>]*> f123 2000 beqz s0,000032a4 <foo\+0x32a4> +[0-9a-f]+ <[^>]*> f123 2020 beqz s0,000032a8 <foo\+0x32a8> +[0-9a-f]+ <[^>]*> f123 2040 beqz s0,000032ac <foo\+0x32ac> +[0-9a-f]+ <[^>]*> f123 2060 beqz s0,000032b0 <foo\+0x32b0> +[0-9a-f]+ <[^>]*> f123 2080 beqz s0,000032b4 <foo\+0x32b4> +[0-9a-f]+ <[^>]*> f123 20a0 beqz s0,000032b8 <foo\+0x32b8> +[0-9a-f]+ <[^>]*> f123 20c0 beqz s0,000032bc <foo\+0x32bc> +[0-9a-f]+ <[^>]*> f123 20e0 beqz s0,000032c0 <foo\+0x32c0> +[0-9a-f]+ <[^>]*> f123 2800 bnez s0,000032c4 <foo\+0x32c4> +[0-9a-f]+ <[^>]*> f123 2820 bnez s0,000032c8 <foo\+0x32c8> +[0-9a-f]+ <[^>]*> f123 2840 bnez s0,000032cc <foo\+0x32cc> +[0-9a-f]+ <[^>]*> f123 2860 bnez s0,000032d0 <foo\+0x32d0> +[0-9a-f]+ <[^>]*> f123 2880 bnez s0,000032d4 <foo\+0x32d4> +[0-9a-f]+ <[^>]*> f123 28a0 bnez s0,000032d8 <foo\+0x32d8> +[0-9a-f]+ <[^>]*> f123 28c0 bnez s0,000032dc <foo\+0x32dc> +[0-9a-f]+ <[^>]*> f123 28e0 bnez s0,000032e0 <foo\+0x32e0> +[0-9a-f]+ <[^>]*> f123 3000 sll s0,4 +[0-9a-f]+ <[^>]*> f123 3004 sll s0,4 +[0-9a-f]+ <[^>]*> f123 3008 sll s0,4 +[0-9a-f]+ <[^>]*> f123 300c sll s0,4 +[0-9a-f]+ <[^>]*> f123 3010 sll s0,4 +[0-9a-f]+ <[^>]*> f123 3014 sll s0,4 +[0-9a-f]+ <[^>]*> f123 3018 sll s0,4 +[0-9a-f]+ <[^>]*> f123 301c sll s0,4 +[0-9a-f]+ <[^>]*> f123 3001 dsll s0,36 +[0-9a-f]+ <[^>]*> f123 3005 dsll s0,36 +[0-9a-f]+ <[^>]*> f123 3009 dsll s0,36 +[0-9a-f]+ <[^>]*> f123 300d dsll s0,36 +[0-9a-f]+ <[^>]*> f123 3011 dsll s0,36 +[0-9a-f]+ <[^>]*> f123 3015 dsll s0,36 +[0-9a-f]+ <[^>]*> f123 3019 dsll s0,36 +[0-9a-f]+ <[^>]*> f123 301d dsll s0,36 +[0-9a-f]+ <[^>]*> f123 3002 srl s0,4 +[0-9a-f]+ <[^>]*> f123 3006 srl s0,4 +[0-9a-f]+ <[^>]*> f123 300a srl s0,4 +[0-9a-f]+ <[^>]*> f123 300e srl s0,4 +[0-9a-f]+ <[^>]*> f123 3012 srl s0,4 +[0-9a-f]+ <[^>]*> f123 3016 srl s0,4 +[0-9a-f]+ <[^>]*> f123 301a srl s0,4 +[0-9a-f]+ <[^>]*> f123 301e srl s0,4 +[0-9a-f]+ <[^>]*> f123 3003 sra s0,4 +[0-9a-f]+ <[^>]*> f123 3007 sra s0,4 +[0-9a-f]+ <[^>]*> f123 300b sra s0,4 +[0-9a-f]+ <[^>]*> f123 300f sra s0,4 +[0-9a-f]+ <[^>]*> f123 3013 sra s0,4 +[0-9a-f]+ <[^>]*> f123 3017 sra s0,4 +[0-9a-f]+ <[^>]*> f123 301b sra s0,4 +[0-9a-f]+ <[^>]*> f123 301f sra s0,4 +[0-9a-f]+ <[^>]*> f123 3800 ld s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 4000 addiu s0,s0,6432 +[0-9a-f]+ <[^>]*> f123 4010 daddiu s0,s0,6432 +[0-9a-f]+ <[^>]*> f123 4800 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 4820 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 4840 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 4860 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 4880 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 48a0 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 48c0 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 48e0 addiu s0,6432 +[0-9a-f]+ <[^>]*> f123 5000 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 5020 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 5040 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 5060 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 5080 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 50a0 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 50c0 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 50e0 slti s0,6432 +[0-9a-f]+ <[^>]*> f123 5800 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 5820 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 5840 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 5860 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 5880 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 58a0 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 58c0 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 58e0 sltiu s0,6432 +[0-9a-f]+ <[^>]*> f123 6000 bteqz 000033d0 <foo\+0x33d0> +[0-9a-f]+ <[^>]*> f123 6020 bteqz 000033d4 <foo\+0x33d4> +[0-9a-f]+ <[^>]*> f123 6040 bteqz 000033d8 <foo\+0x33d8> +[0-9a-f]+ <[^>]*> f123 6060 bteqz 000033dc <foo\+0x33dc> +[0-9a-f]+ <[^>]*> f123 6080 bteqz 000033e0 <foo\+0x33e0> +[0-9a-f]+ <[^>]*> f123 60a0 bteqz 000033e4 <foo\+0x33e4> +[0-9a-f]+ <[^>]*> f123 60c0 bteqz 000033e8 <foo\+0x33e8> +[0-9a-f]+ <[^>]*> f123 60e0 bteqz 000033ec <foo\+0x33ec> +[0-9a-f]+ <[^>]*> f123 6100 btnez 000033f0 <foo\+0x33f0> +[0-9a-f]+ <[^>]*> f123 6120 btnez 000033f4 <foo\+0x33f4> +[0-9a-f]+ <[^>]*> f123 6140 btnez 000033f8 <foo\+0x33f8> +[0-9a-f]+ <[^>]*> f123 6160 btnez 000033fc <foo\+0x33fc> +[0-9a-f]+ <[^>]*> f123 6180 btnez 00003400 <foo\+0x3400> +[0-9a-f]+ <[^>]*> f123 61a0 btnez 00003404 <foo\+0x3404> +[0-9a-f]+ <[^>]*> f123 61c0 btnez 00003408 <foo\+0x3408> +[0-9a-f]+ <[^>]*> f123 61e0 btnez 0000340c <foo\+0x340c> +[0-9a-f]+ <[^>]*> f123 6200 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 6220 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 6240 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 6280 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 62a0 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 62c0 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 62e0 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 6200 sw ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 6300 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 6320 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 6340 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 6360 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 6380 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 63a0 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 63c0 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 63e0 addiu sp,6432 +[0-9a-f]+ <[^>]*> f123 6400 restore 256,s2,a1-a3 +[0-9a-f]+ <[^>]*> f123 6480 save 256,s2,a1-a3 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> 6500 nop +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> 6501 move zero,s1 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> 6700 move s0,zero +[0-9a-f]+ <[^>]*> f123 6800 li s0,6432 +[0-9a-f]+ <[^>]*> f123 6820 li s0,6432 +[0-9a-f]+ <[^>]*> f123 6840 li s0,6432 +[0-9a-f]+ <[^>]*> f123 6860 li s0,6432 +[0-9a-f]+ <[^>]*> f123 6880 li s0,6432 +[0-9a-f]+ <[^>]*> f123 68a0 li s0,6432 +[0-9a-f]+ <[^>]*> f123 68c0 li s0,6432 +[0-9a-f]+ <[^>]*> f123 68e0 li s0,6432 +[0-9a-f]+ <[^>]*> f123 7000 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 7020 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 7040 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 7060 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 7080 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 70a0 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 70c0 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 70e0 cmpi s0,6432 +[0-9a-f]+ <[^>]*> f123 7800 sd s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 8000 lb s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 8800 lh s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 9000 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 9020 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 9040 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 9060 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 9080 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 90a0 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 90c0 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 90e0 lw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 9800 lw s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 a000 lbu s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 a800 lhu s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 b000 lw s0,00001bb8 <foo\+0x1bb8> +[0-9a-f]+ <[^>]*> f123 b020 lw s0,00001bbc <foo\+0x1bbc> +[0-9a-f]+ <[^>]*> f123 b040 lw s0,00001bc0 <foo\+0x1bc0> +[0-9a-f]+ <[^>]*> f123 b060 lw s0,00001bc4 <foo\+0x1bc4> +[0-9a-f]+ <[^>]*> f123 b080 lw s0,00001bc8 <foo\+0x1bc8> +[0-9a-f]+ <[^>]*> f123 b0a0 lw s0,00001bcc <foo\+0x1bcc> +[0-9a-f]+ <[^>]*> f123 b0c0 lw s0,00001bd0 <foo\+0x1bd0> +[0-9a-f]+ <[^>]*> f123 b0e0 lw s0,00001bd4 <foo\+0x1bd4> +[0-9a-f]+ <[^>]*> f123 b800 lwu s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 c000 sb s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 c800 sh s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 d000 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d020 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d040 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d060 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d080 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d0a0 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d0c0 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d0e0 sw s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 d800 sw s0,6432\(s0\) +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e000 daddu s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e001 addu s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e002 dsubu s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e003 subu s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e800 jr s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e820 jr ra +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e840 jalr s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e880 jrc s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e8a0 jrc ra +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e8c0 jalrc s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e801 sdbbp 0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e802 slt s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e803 sltu s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e804 sllv s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e805 break 0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e806 srlv s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e807 srav s0,s0 +[0-9a-f]+ <[^>]*> f123 e808 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 e908 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 ea08 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 eb08 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 ec08 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 ed08 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 ee08 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 ef08 dsrl s0,36 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e809 entry +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e829 entry ra +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> ed09 exit \$f0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> ee09 exit \$f0-\$f1 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> ef09 exit +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e80a cmp s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e80b neg s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e80c and s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e80d or s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e80e xor s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e80f not s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e810 mfhi s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e811 zeb s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e831 zeh s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e851 zew s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e891 seb s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e8b1 seh s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e8d1 sew s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e812 mflo s0 +[0-9a-f]+ <[^>]*> f123 e813 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 e913 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 ea13 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 eb13 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 ec13 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 ed13 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 ee13 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 ef13 dsra s0,36 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e814 dsllv s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e816 dsrlv s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e817 dsrav s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e818 mult s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e819 multu s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e81a div zero,s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e81b divu zero,s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e81c dmult s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e81d dmultu s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e81e ddiv zero,s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e81f ddivu zero,s0,s0 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> f000 extend 0x0 +[0-9a-f]+ <[^>]*> f123 f800 ld s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 f900 sd s0,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fa00 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fa20 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fa40 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fa60 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fa80 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 faa0 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fac0 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fae0 sd ra,6432\(sp\) +[0-9a-f]+ <[^>]*> f123 fb00 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fb20 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fb40 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fb60 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fb80 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fba0 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fbc0 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fbe0 daddiu sp,6432 +[0-9a-f]+ <[^>]*> f123 fc00 ld s0,00001d50 <foo\+0x1d50> +[0-9a-f]+ <[^>]*> f123 fd00 daddiu s0,6432 +[0-9a-f]+ <[^>]*> f123 fe00 dla s0,00001d58 <foo\+0x1d58> +[0-9a-f]+ <[^>]*> f123 ff00 daddiu s0,sp,6432 + \.\.\. diff --git a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.s b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.s new file mode 100644 index 0000000..bb86f22 --- /dev/null +++ b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.s @@ -0,0 +1,630 @@ + .set mips16 + .set noreorder +foo: + extend 0x123 # ADDIUSP + addiu $16, $29, 0 + extend 0x123 + addiu $16, $29, 128 + extend 0x123 + addiu $16, $29, 256 + extend 0x123 + addiu $16, $29, 384 + extend 0x123 + addiu $16, $29, 512 + extend 0x123 + addiu $16, $29, 640 + extend 0x123 + addiu $16, $29, 768 + extend 0x123 + addiu $16, $29, 896 + + extend 0x123 # ADDIUPC + addiu $16, $pc, 0 + extend 0x123 + addiu $16, $pc, 128 + extend 0x123 + addiu $16, $pc, 256 + extend 0x123 + addiu $16, $pc, 384 + extend 0x123 + addiu $16, $pc, 512 + extend 0x123 + addiu $16, $pc, 640 + extend 0x123 + addiu $16, $pc, 768 + extend 0x123 + addiu $16, $pc, 896 + + extend 0x123 # B + b . + 2 + extend 0x123 + b . + 66 + extend 0x123 + b . + 130 + extend 0x123 + b . + 194 + extend 0x123 + b . + 258 + extend 0x123 + b . + 322 + extend 0x123 + b . + 386 + extend 0x123 + b . + 450 + + extend 0x123 # BEQZ + beqz $16, . + 2 + extend 0x123 + beqz $16, . + 66 + extend 0x123 + beqz $16, . + 130 + extend 0x123 + beqz $16, . + 194 + extend 0x123 + beqz $16, . - 254 + extend 0x123 + beqz $16, . - 190 + extend 0x123 + beqz $16, . - 126 + extend 0x123 + beqz $16, . - 62 + + extend 0x123 # BNEZ + bnez $16, . + 2 + extend 0x123 + bnez $16, . + 66 + extend 0x123 + bnez $16, . + 130 + extend 0x123 + bnez $16, . + 194 + extend 0x123 + bnez $16, . - 254 + extend 0x123 + bnez $16, . - 190 + extend 0x123 + bnez $16, . - 126 + extend 0x123 + bnez $16, . - 62 + + extend 0x123 # SHIFT # SLL + sll $16, $16, 8 + extend 0x123 + sll $16, $16, 1 + extend 0x123 + sll $16, $16, 2 + extend 0x123 + sll $16, $16, 3 + extend 0x123 + sll $16, $16, 4 + extend 0x123 + sll $16, $16, 5 + extend 0x123 + sll $16, $16, 6 + extend 0x123 + sll $16, $16, 7 + + extend 0x123 # DSLL + dsll $16, $16, 8 + extend 0x123 + dsll $16, $16, 1 + extend 0x123 + dsll $16, $16, 2 + extend 0x123 + dsll $16, $16, 3 + extend 0x123 + dsll $16, $16, 4 + extend 0x123 + dsll $16, $16, 5 + extend 0x123 + dsll $16, $16, 6 + extend 0x123 + dsll $16, $16, 7 + + extend 0x123 # SRL + srl $16, $16, 8 + extend 0x123 + srl $16, $16, 1 + extend 0x123 + srl $16, $16, 2 + extend 0x123 + srl $16, $16, 3 + extend 0x123 + srl $16, $16, 4 + extend 0x123 + srl $16, $16, 5 + extend 0x123 + srl $16, $16, 6 + extend 0x123 + srl $16, $16, 7 + + extend 0x123 # SRA + sra $16, $16, 8 + extend 0x123 + sra $16, $16, 1 + extend 0x123 + sra $16, $16, 2 + extend 0x123 + sra $16, $16, 3 + extend 0x123 + sra $16, $16, 4 + extend 0x123 + sra $16, $16, 5 + extend 0x123 + sra $16, $16, 6 + extend 0x123 + sra $16, $16, 7 + + extend 0x123 # LD + ld $16, 0($16) + + extend 0x123 # RRI-A # ADDIU + addiu $16, $16, 0 + extend 0x123 # DADDIU + daddiu $16, $16, 0 + + extend 0x123 # ADDIU8 + addiu $16, 0 + extend 0x123 + addiu $16, 32 + extend 0x123 + addiu $16, 64 + extend 0x123 + addiu $16, 96 + extend 0x123 + addiu $16, -128 + extend 0x123 + addiu $16, -96 + extend 0x123 + addiu $16, -64 + extend 0x123 + addiu $16, -32 + + extend 0x123 # SLTI + slti $16, 0 + extend 0x123 + slti $16, 32 + extend 0x123 + slti $16, 64 + extend 0x123 + slti $16, 96 + extend 0x123 + slti $16, 128 + extend 0x123 + slti $16, 160 + extend 0x123 + slti $16, 192 + extend 0x123 + slti $16, 224 + + extend 0x123 # SLTIU + sltiu $16, 0 + extend 0x123 + sltiu $16, 32 + extend 0x123 + sltiu $16, 64 + extend 0x123 + sltiu $16, 96 + extend 0x123 + sltiu $16, 128 + extend 0x123 + sltiu $16, 160 + extend 0x123 + sltiu $16, 192 + extend 0x123 + sltiu $16, 224 + + extend 0x123 # I8 # BTEQZ + bteqz . + 2 + extend 0x123 + bteqz . + 66 + extend 0x123 + bteqz . + 130 + extend 0x123 + bteqz . + 194 + extend 0x123 + bteqz . - 254 + extend 0x123 + bteqz . - 190 + extend 0x123 + bteqz . - 126 + extend 0x123 + bteqz . - 62 + + extend 0x123 # BTNEZ + btnez . + 2 + extend 0x123 + btnez . + 66 + extend 0x123 + btnez . + 130 + extend 0x123 + btnez . + 194 + extend 0x123 + btnez . - 254 + extend 0x123 + btnez . - 190 + extend 0x123 + btnez . - 126 + extend 0x123 + btnez . - 62 + + extend 0x123 # SWRASP + sw $31, 0($29) + extend 0x123 + sw $31, 128($29) + extend 0x123 + sw $31, 256($29) + extend 0x123 + sw $31, 512($29) + extend 0x123 + sw $31, 640($29) + extend 0x123 + sw $31, 768($29) + extend 0x123 + sw $31, 896($29) + extend 0x123 + sw $31, 0($29) + + extend 0x123 # ADJSP + addiu $29, 0 + extend 0x123 + addiu $29, 256 + extend 0x123 + addiu $29, 512 + extend 0x123 + addiu $29, 768 + extend 0x123 + addiu $29, -1024 + extend 0x123 + addiu $29, -768 + extend 0x123 + addiu $29, -512 + extend 0x123 + addiu $29, -256 + + extend 0x123 # SVRS # RESTORE + restore 128 + extend 0x123 # SAVE + save 128 + + extend 0x123 # MOV32R + move $0, $16 + extend 0x123 + move $0, $17 + + extend 0x123 # MOVR32 + move $16, $0 + + extend 0x123 # LI + li $16, 0 + extend 0x123 + li $16, 32 + extend 0x123 + li $16, 64 + extend 0x123 + li $16, 96 + extend 0x123 + li $16, 128 + extend 0x123 + li $16, 160 + extend 0x123 + li $16, 192 + extend 0x123 + li $16, 224 + + extend 0x123 # CMPI + cmpi $16, 0 + extend 0x123 + cmpi $16, 32 + extend 0x123 + cmpi $16, 64 + extend 0x123 + cmpi $16, 96 + extend 0x123 + cmpi $16, 128 + extend 0x123 + cmpi $16, 160 + extend 0x123 + cmpi $16, 192 + extend 0x123 + cmpi $16, 224 + + extend 0x123 # SD + sd $16, 0($16) + + extend 0x123 # LB + lb $16, 0($16) + + extend 0x123 # LH + lh $16, 0($16) + + extend 0x123 # LWSP + lw $16, 0($29) + extend 0x123 + lw $16, 128($29) + extend 0x123 + lw $16, 256($29) + extend 0x123 + lw $16, 384($29) + extend 0x123 + lw $16, 512($29) + extend 0x123 + lw $16, 640($29) + extend 0x123 + lw $16, 768($29) + extend 0x123 + lw $16, 896($29) + + extend 0x123 # LW + lw $16, 0($16) + + extend 0x123 # LBU + lbu $16, 0($16) + + extend 0x123 # LHU + lhu $16, 0($16) + + extend 0x123 # LWPC + lw $16, 0($pc) + extend 0x123 + lw $16, 128($pc) + extend 0x123 + lw $16, 256($pc) + extend 0x123 + lw $16, 384($pc) + extend 0x123 + lw $16, 512($pc) + extend 0x123 + lw $16, 640($pc) + extend 0x123 + lw $16, 768($pc) + extend 0x123 + lw $16, 896($pc) + + extend 0x123 # LWU + lwu $16, 0($16) + + extend 0x123 # SB + sb $16, 0($16) + + extend 0x123 # SH + sh $16, 0($16) + + extend 0x123 # SWSP + sw $16, 0($29) + extend 0x123 + sw $16, 128($29) + extend 0x123 + sw $16, 256($29) + extend 0x123 + sw $16, 384($29) + extend 0x123 + sw $16, 512($29) + extend 0x123 + sw $16, 640($29) + extend 0x123 + sw $16, 768($29) + extend 0x123 + sw $16, 896($29) + + extend 0x123 # SW + sw $16, 0($16) + + extend 0x123 # RRR # DADDU + daddu $16, $16, $16 + + extend 0x123 # ADDU + addu $16, $16, $16 + + extend 0x123 # DSUBU + dsubu $16, $16, $16 + + extend 0x123 # SUBU + subu $16, $16, $16 + + extend 0x123 # RR # J(AL)R(C) # JR rx + jr $16 + extend 0x123 # JR ra + jr $31 + extend 0x123 # JALR + jalr $16 + extend 0x123 # JRC rx + jrc $16 + extend 0x123 # JRC ra + jrc $31 + extend 0x123 # JALRC + jalrc $16 + + extend 0x123 # SDBBP + sdbbp 0 + + extend 0x123 # SLT + slt $16, $16 + + extend 0x123 # SLTU + sltu $16, $16 + + extend 0x123 # SLLV + sllv $16, $16 + + extend 0x123 # BREAK + break 0 + + extend 0x123 # SRLV + srlv $16, $16 + + extend 0x123 # SRAV + srav $16, $16 + + extend 0x123 # DSRL + dsrl $16, 8 + extend 0x123 + dsrl $16, 1 + extend 0x123 + dsrl $16, 2 + extend 0x123 + dsrl $16, 3 + extend 0x123 + dsrl $16, 4 + extend 0x123 + dsrl $16, 5 + extend 0x123 + dsrl $16, 6 + extend 0x123 + dsrl $16, 7 + + extend 0x123 # ENTRY/EXIT + entry + extend 0x123 + entry $31 + extend 0x123 + exit $f0 + extend 0x123 + exit $f0-$f1 + extend 0x123 + exit + + extend 0x123 # CMP + cmp $16, $16 + + extend 0x123 # NEG + neg $16, $16 + + extend 0x123 # AND + and $16, $16 + + extend 0x123 # OR + or $16, $16 + + extend 0x123 # XOR + xor $16, $16 + + extend 0x123 # NOT + not $16, $16 + + extend 0x123 # MFHI + mfhi $16 + + extend 0x123 # CNVT # ZEB + zeb $16 + extend 0x123 # ZEH + zeh $16 + extend 0x123 # ZEW + zew $16 + extend 0x123 # SEB + seb $16 + extend 0x123 # SEH + seh $16 + extend 0x123 # SEW + sew $16 + + extend 0x123 # MFLO + mflo $16 + + extend 0x123 # DSRA + dsra $16, 8 + extend 0x123 + dsra $16, 1 + extend 0x123 + dsra $16, 2 + extend 0x123 + dsra $16, 3 + extend 0x123 + dsra $16, 4 + extend 0x123 + dsra $16, 5 + extend 0x123 + dsra $16, 6 + extend 0x123 + dsra $16, 7 + + extend 0x123 # DSLLV + dsllv $16, $16 + + extend 0x123 # DSRLV + dsrlv $16, $16 + + extend 0x123 # DSRAV + dsrav $16, $16 + + extend 0x123 # MULT + mult $16, $16 + + extend 0x123 # MULTU + multu $16, $16 + + extend 0x123 # DIV + div $0, $16, $16 + + extend 0x123 # DIVU + divu $0, $16, $16 + + extend 0x123 # DMULT + dmult $16, $16 + + extend 0x123 # DMULTU + dmultu $16, $16 + + extend 0x123 # DDIV + ddiv $0, $16, $16 + + extend 0x123 # DDIVU + ddivu $0, $16, $16 + + extend 0x123 # EXTEND + extend 0 + + extend 0x123 # I64 # LDSP + ld $16, 0($29) + + extend 0x123 # SDSP + sd $16, 0($29) + + extend 0x123 # SDRASP + sd $31, 0($29) + extend 0x123 + sd $31, 256($29) + extend 0x123 + sd $31, 512($29) + extend 0x123 + sd $31, 768($29) + extend 0x123 + sd $31, 1024($29) + extend 0x123 + sd $31, 1280($29) + extend 0x123 + sd $31, 1536($29) + extend 0x123 + sd $31, 1792($29) + + extend 0x123 # DADJSP + daddiu $29, 0 + extend 0x123 + daddiu $29, 256 + extend 0x123 + daddiu $29, 512 + extend 0x123 + daddiu $29, 768 + extend 0x123 + daddiu $29, -1024 + extend 0x123 + daddiu $29, -768 + extend 0x123 + daddiu $29, -512 + extend 0x123 + daddiu $29, -256 + + extend 0x123 # LDPC + ld $16, 0($pc) + + extend 0x123 # DADDIU5 + daddiu $16, 0 + + extend 0x123 # DADDIUPC + daddiu $16, $pc, 0 + + extend 0x123 # DADDIUSP + daddiu $16, $sp, 0 + +# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 4, 0 + .space 16 diff --git a/gas/ChangeLog b/gas/ChangeLog index f5dd23d..2a2fafb 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,42 @@ 2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + * config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix + instruction size override for INSN2_SHORT_ONLY opcode table + entries. + * testsuite/gas/mips/mips16-extend-swap.d: Adjust output. + * testsuite/gas/mips/mips16-macro-e.l: Adjust error messages. + * testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error + messages. + * testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error + messages. + * testsuite/gas/mips/mips16-insn-e.d: New test. + * testsuite/gas/mips/mips16-insn-t.d: New test. + * testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test. + * testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test. + * testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test. + * testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test. + * testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test. + * testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test. + * testsuite/gas/mips/mips16-insn-e.l: New stderr output. + * testsuite/gas/mips/mips16-insn-t.l: New stderr output. + * testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr + output. + * testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr + output. + * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr + output. + * testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr + output. + * testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr + output. + * testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr + output. + * testsuite/gas/mips/mips16-insn-e.s: New test source. + * testsuite/gas/mips/mips16-insn-t.s: New test source. + * testsuite/gas/mips/mips.exp: Run the new tests. + +2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + * config/tc-mips.c (match_mips16_insn): Remove the `6' operand code special case and its associated comment. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 7105604..562da64 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -3293,6 +3293,8 @@ is_size_valid_16 (const struct mips_opcode *mo) return FALSE; if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) return FALSE; + if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) + return FALSE; return TRUE; } diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index a5c722c..60d956d 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -877,6 +877,10 @@ if { [istarget mips*-*-vxworks*] } { [mips_arch_list_matching mips16-32] run_dump_test_arches "mips16-macro-e" \ [mips_arch_list_matching mips16-32] + run_dump_test_arches "mips16-insn-t" \ + [mips_arch_list_matching mips16-32] + run_dump_test_arches "mips16-insn-e" \ + [mips_arch_list_matching mips16-32] # Check MIPS16e extensions run_dump_test_arches "mips16e" [mips_arch_list_matching mips16e-32] run_dump_test_arches "mips16e-64" [mips_arch_list_matching mips16e-32] diff --git a/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.d b/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.d new file mode 100644 index 0000000..28e2f32 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.d @@ -0,0 +1,4 @@ +#as: -32 +#name: MIPS16 explicit extended instructions +#error-output: mips16-32@mips16-insn-e.l +#source: mips16-insn-e.s diff --git a/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.l b/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.l new file mode 100644 index 0000000..0d43204 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-32@mips16-insn-e.l @@ -0,0 +1,133 @@ +.*: Assembler messages: +.*:4: Warning: extended operand requested but not required +.*:5: Warning: extended operand requested but not required +.*:8: Warning: extended operand requested but not required +.*:9: Warning: extended operand requested but not required +.*:23: Warning: extended operand requested but not required +.*:24: Error: opcode not supported on this processor: mips1 \(mips1\) `dsll\.e \$16,\$16,8' +.*:25: Warning: extended operand requested but not required +.*:26: Warning: extended operand requested but not required +.*:28: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.e \$16,0\(\$16\)' +.*:30: Warning: extended operand requested but not required +.*:31: Warning: extended operand requested but not required +.*:32: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$16,\$16,0' +.*:33: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,\$16,0' +.*:35: Warning: extended operand requested but not required +.*:36: Warning: extended operand requested but not required +.*:38: Warning: extended operand requested but not required +.*:39: Warning: extended operand requested but not required +.*:41: Warning: extended operand requested but not required +.*:42: Warning: extended operand requested but not required +.*:46: Warning: extended operand requested but not required +.*:47: Warning: extended operand requested but not required +.*:48: Warning: extended operand requested but not required +.*:49: Warning: extended operand requested but not required +.*:50: Warning: extended operand requested but not required +.*:51: Error: opcode not supported on this processor: mips1 \(mips1\) `restore\.e 128' +.*:52: Error: opcode not supported on this processor: mips1 \(mips1\) `save\.e 128' +.*:53: Error: unrecognized extended version of MIPS16 opcode `nop\.e ' +.*:54: Error: unrecognized extended version of MIPS16 opcode `move\.e \$0,\$16' +.*:55: Error: unrecognized extended version of MIPS16 opcode `move\.e \$16,\$0' +.*:57: Warning: extended operand requested but not required +.*:59: Warning: extended operand requested but not required +.*:60: Warning: extended operand requested but not required +.*:62: Error: opcode not supported on this processor: mips1 \(mips1\) `sd\.e \$16,0\(\$16\)' +.*:64: Warning: extended operand requested but not required +.*:66: Warning: extended operand requested but not required +.*:68: Warning: extended operand requested but not required +.*:70: Warning: extended operand requested but not required +.*:72: Warning: extended operand requested but not required +.*:74: Warning: extended operand requested but not required +.*:77: Warning: extended operand requested but not required +.*:80: Error: opcode not supported on this processor: mips1 \(mips1\) `lwu\.e \$16,0\(\$16\)' +.*:82: Warning: extended operand requested but not required +.*:84: Warning: extended operand requested but not required +.*:86: Warning: extended operand requested but not required +.*:88: Warning: extended operand requested but not required +.*:90: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,\$16,\$16' +.*:91: Error: invalid operands `addu\.e \$16,\$16,\$16' +.*:92: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu\.e \$16,\$16,\$16' +.*:93: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$16,\$16,\$16' +.*:95: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$16' +.*:97: Error: unrecognized extended version of MIPS16 opcode `j\.e \$16' +.*:99: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$31' +.*:101: Error: unrecognized extended version of MIPS16 opcode `j\.e \$31' +.*:103: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$16' +.*:105: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$31,\$16' +.*:107: Error: operand 1 must be an immediate expression `jal\.e \$16' +.*:109: Error: operand 1 must be an immediate expression `jal\.e \$31,\$16' +.*:111: Error: opcode not supported on this processor: mips1 \(mips1\) `jrc\.e \$16' +.*:112: Error: opcode not supported on this processor: mips1 \(mips1\) `jrc\.e \$31' +.*:113: Error: opcode not supported on this processor: mips1 \(mips1\) `jalrc\.e \$16' +.*:114: Error: opcode not supported on this processor: mips1 \(mips1\) `jalrc\.e \$31,\$16' +.*:115: Error: opcode not supported on this processor: mips1 \(mips1\) `sdbbp\.e 0' +.*:116: Error: invalid operands `slt\.e \$16,\$16' +.*:117: Error: invalid operands `sltu\.e \$16,\$16' +.*:118: Error: unrecognized extended version of MIPS16 opcode `sllv\.e \$16,\$16' +.*:119: Error: invalid operands `sll\.e \$16,\$16' +.*:120: Error: unrecognized extended version of MIPS16 opcode `break\.e 0' +.*:121: Error: unrecognized extended version of MIPS16 opcode `srlv\.e \$16,\$16' +.*:122: Error: invalid operands `srl\.e \$16,\$16' +.*:123: Error: unrecognized extended version of MIPS16 opcode `srav\.e \$16,\$16' +.*:124: Error: invalid operands `sra\.e \$16,\$16' +.*:125: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrl\.e \$16,8' +.*:126: Error: unrecognized extended version of MIPS16 opcode `entry\.e ' +.*:127: Error: unrecognized extended version of MIPS16 opcode `entry\.e \$31' +.*:128: Error: unrecognized extended version of MIPS16 opcode `exit\.e \$f0' +.*:129: Error: unrecognized extended version of MIPS16 opcode `exit\.e' +.*:130: Error: invalid operands `cmp\.e \$16,\$16' +.*:131: Error: unrecognized extended version of MIPS16 opcode `neg\.e \$16,\$16' +.*:132: Error: unrecognized extended version of MIPS16 opcode `and\.e \$16,\$16' +.*:133: Error: unrecognized extended version of MIPS16 opcode `or\.e \$16,\$16' +.*:134: Error: unrecognized extended version of MIPS16 opcode `xor\.e \$16,\$16' +.*:135: Error: unrecognized extended version of MIPS16 opcode `not\.e \$16,\$16' +.*:136: Error: unrecognized extended version of MIPS16 opcode `mfhi\.e \$16' +.*:137: Error: opcode not supported on this processor: mips1 \(mips1\) `zeb\.e \$16' +.*:138: Error: opcode not supported on this processor: mips1 \(mips1\) `zeh\.e \$16' +.*:139: Error: opcode not supported on this processor: mips1 \(mips1\) `zew\.e \$16' +.*:140: Error: opcode not supported on this processor: mips1 \(mips1\) `seb\.e \$16' +.*:141: Error: opcode not supported on this processor: mips1 \(mips1\) `seh\.e \$16' +.*:142: Error: opcode not supported on this processor: mips1 \(mips1\) `sew\.e \$16' +.*:143: Error: unrecognized extended version of MIPS16 opcode `mflo\.e \$16' +.*:144: Error: opcode not supported on this processor: mips1 \(mips1\) `dsra\.e \$16,8' +.*:145: Error: opcode not supported on this processor: mips1 \(mips1\) `dsllv\.e \$16,\$16' +.*:146: Error: opcode not supported on this processor: mips1 \(mips1\) `dsll\.e \$16,\$16' +.*:147: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrlv\.e \$16,\$16' +.*:148: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrl\.e \$16,\$16' +.*:149: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrav\.e \$16,\$16' +.*:150: Error: opcode not supported on this processor: mips1 \(mips1\) `dsra\.e \$16,\$16' +.*:151: Error: unrecognized extended version of MIPS16 opcode `mult\.e \$16,\$16' +.*:152: Error: unrecognized extended version of MIPS16 opcode `multu\.e \$16,\$16' +.*:153: Error: unrecognized extended version of MIPS16 opcode `div\.e \$0,\$16,\$16' +.*:154: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$0,\$16,\$16' +.*:155: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$0,\$16,\$16' +.*:156: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$0,\$16,\$16' +.*:157: Error: opcode not supported on this processor: mips1 \(mips1\) `dmult\.e \$16,\$16' +.*:158: Error: opcode not supported on this processor: mips1 \(mips1\) `dmultu\.e \$16,\$16' +.*:159: Error: opcode not supported on this processor: mips1 \(mips1\) `ddiv\.e \$0,\$16,\$16' +.*:160: Error: opcode not supported on this processor: mips1 \(mips1\) `drem\.e \$0,\$16,\$16' +.*:161: Error: opcode not supported on this processor: mips1 \(mips1\) `ddivu\.e \$0,\$16,\$16' +.*:162: Error: opcode not supported on this processor: mips1 \(mips1\) `dremu\.e \$0,\$16,\$16' +.*:164: Error: unrecognized extended version of MIPS16 opcode `extend\.e 0' +.*:166: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.e \$16,0\(\$29\)' +.*:167: Error: opcode not supported on this processor: mips1 \(mips1\) `sd\.e \$16,0\(\$29\)' +.*:168: Error: opcode not supported on this processor: mips1 \(mips1\) `sd\.e \$31,0\(\$29\)' +.*:169: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$29,0' +.*:170: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$29,\$29,0' +.*:171: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$29,0' +.*:172: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$29,\$29,0' +.*:174: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.e \$16,0\(\$pc\)' +.*:175: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.e \$16,\.-3' +.*:176: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$16,0' +.*:177: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,0' +.*:179: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$16,\$pc,0' +.*:180: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,\$pc,0' +.*:181: Error: opcode not supported on this processor: mips1 \(mips1\) `dla\.e \$16,\.-1' +.*:182: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.e \$16,\$sp,0' +.*:183: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.e \$16,\$sp,0' +.*:10: Warning: extended operand requested but not required +.*:12: Warning: extended operand requested but not required +.*:19: Warning: extended operand requested but not required +.*:21: Warning: extended operand requested but not required +.*:44: Warning: extended operand requested but not required +.*:45: Warning: extended operand requested but not required diff --git a/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.d b/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.d new file mode 100644 index 0000000..499e6aa --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.d @@ -0,0 +1,4 @@ +#as: -32 +#name: MIPS16 explicit unextended instructions +#error-output: mips16-32@mips16-insn-t.l +#source: mips16-insn-t.s diff --git a/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.l b/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.l new file mode 100644 index 0000000..a632d59 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-32@mips16-insn-t.l @@ -0,0 +1,54 @@ +.*: Assembler messages: +.*:14: Error: invalid operands `jal\.t 0' +.*:16: Error: unrecognized unextended version of MIPS16 opcode `jalx\.t 0' +.*:24: Error: opcode not supported on this processor: mips1 \(mips1\) `dsll\.t \$16,\$16,8' +.*:28: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.t \$16,0\(\$16\)' +.*:32: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$16,\$16,0' +.*:33: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,\$16,0' +.*:51: Error: opcode not supported on this processor: mips1 \(mips1\) `restore\.t 128' +.*:52: Error: opcode not supported on this processor: mips1 \(mips1\) `save\.t 128' +.*:62: Error: opcode not supported on this processor: mips1 \(mips1\) `sd\.t \$16,0\(\$16\)' +.*:80: Error: opcode not supported on this processor: mips1 \(mips1\) `lwu\.t \$16,0\(\$16\)' +.*:90: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,\$16,\$16' +.*:92: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu\.t \$16,\$16,\$16' +.*:111: Error: opcode not supported on this processor: mips1 \(mips1\) `jrc\.t \$16' +.*:112: Error: opcode not supported on this processor: mips1 \(mips1\) `jrc\.t \$31' +.*:113: Error: opcode not supported on this processor: mips1 \(mips1\) `jalrc\.t \$16' +.*:114: Error: opcode not supported on this processor: mips1 \(mips1\) `jalrc\.t \$31,\$16' +.*:115: Error: opcode not supported on this processor: mips1 \(mips1\) `sdbbp\.t 0' +.*:125: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrl\.t \$16,8' +.*:137: Error: opcode not supported on this processor: mips1 \(mips1\) `zeb\.t \$16' +.*:138: Error: opcode not supported on this processor: mips1 \(mips1\) `zeh\.t \$16' +.*:139: Error: opcode not supported on this processor: mips1 \(mips1\) `zew\.t \$16' +.*:140: Error: opcode not supported on this processor: mips1 \(mips1\) `seb\.t \$16' +.*:141: Error: opcode not supported on this processor: mips1 \(mips1\) `seh\.t \$16' +.*:142: Error: opcode not supported on this processor: mips1 \(mips1\) `sew\.t \$16' +.*:144: Error: opcode not supported on this processor: mips1 \(mips1\) `dsra\.t \$16,8' +.*:145: Error: opcode not supported on this processor: mips1 \(mips1\) `dsllv\.t \$16,\$16' +.*:146: Error: opcode not supported on this processor: mips1 \(mips1\) `dsll\.t \$16,\$16' +.*:147: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrlv\.t \$16,\$16' +.*:148: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrl\.t \$16,\$16' +.*:149: Error: opcode not supported on this processor: mips1 \(mips1\) `dsrav\.t \$16,\$16' +.*:150: Error: opcode not supported on this processor: mips1 \(mips1\) `dsra\.t \$16,\$16' +.*:157: Error: opcode not supported on this processor: mips1 \(mips1\) `dmult\.t \$16,\$16' +.*:158: Error: opcode not supported on this processor: mips1 \(mips1\) `dmultu\.t \$16,\$16' +.*:159: Error: opcode not supported on this processor: mips1 \(mips1\) `ddiv\.t \$0,\$16,\$16' +.*:160: Error: opcode not supported on this processor: mips1 \(mips1\) `drem\.t \$0,\$16,\$16' +.*:161: Error: opcode not supported on this processor: mips1 \(mips1\) `ddivu\.t \$0,\$16,\$16' +.*:162: Error: opcode not supported on this processor: mips1 \(mips1\) `dremu\.t \$0,\$16,\$16' +.*:166: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.t \$16,0\(\$29\)' +.*:167: Error: opcode not supported on this processor: mips1 \(mips1\) `sd\.t \$16,0\(\$29\)' +.*:168: Error: opcode not supported on this processor: mips1 \(mips1\) `sd\.t \$31,0\(\$29\)' +.*:169: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$29,0' +.*:170: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$29,\$29,0' +.*:171: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$29,0' +.*:172: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$29,\$29,0' +.*:174: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.t \$16,0\(\$pc\)' +.*:175: Error: opcode not supported on this processor: mips1 \(mips1\) `ld\.t \$16,\.-3' +.*:176: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$16,0' +.*:177: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,0' +.*:179: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$16,\$pc,0' +.*:180: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,\$pc,0' +.*:181: Error: opcode not supported on this processor: mips1 \(mips1\) `dla\.t \$16,\.-1' +.*:182: Error: opcode not supported on this processor: mips1 \(mips1\) `daddiu\.t \$16,\$sp,0' +.*:183: Error: opcode not supported on this processor: mips1 \(mips1\) `daddu\.t \$16,\$sp,0' diff --git a/gas/testsuite/gas/mips/mips16-32@mips16-macro-e.l b/gas/testsuite/gas/mips/mips16-32@mips16-macro-e.l index ace5989..a66559b 100644 --- a/gas/testsuite/gas/mips/mips16-32@mips16-macro-e.l +++ b/gas/testsuite/gas/mips/mips16-32@mips16-macro-e.l @@ -1,20 +1,20 @@ .*: Assembler messages: -.*:4: Error: invalid operands `div\.e \$2,\$3,\$4' -.*:5: Error: invalid operands `divu\.e \$3,\$4,\$5' +.*:4: Error: unrecognized extended version of MIPS16 opcode `div\.e \$2,\$3,\$4' +.*:5: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$3,\$4,\$5' .*:6: Error: opcode not supported on this processor: mips1 \(mips1\) `ddiv\.e \$4,\$5,\$6' .*:7: Error: opcode not supported on this processor: mips1 \(mips1\) `ddivu\.e \$5,\$6,\$7' -.*:8: Error: invalid operands `rem\.e \$6,\$7,\$16' -.*:9: Error: invalid operands `remu\.e \$6,\$7,\$17' +.*:8: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$6,\$7,\$16' +.*:9: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$6,\$7,\$17' .*:10: Error: opcode not supported on this processor: mips1 \(mips1\) `drem\.e \$2,\$3,\$4' .*:11: Error: opcode not supported on this processor: mips1 \(mips1\) `dremu\.e \$3,\$4,\$5' .*:12: Error: unrecognized extended version of MIPS16 opcode `mul\.e \$4,\$5,\$6' .*:13: Error: opcode not supported on this processor: mips1 \(mips1\) `dmul\.e \$5,\$6,\$7' -.*:14: Error: invalid operands `subu\.e \$2,-32767' -.*:15: Error: invalid operands `subu\.e \$3,16' -.*:16: Error: invalid operands `subu\.e \$4,32768' -.*:17: Error: invalid operands `subu\.e \$3,\$7,-16383' -.*:18: Error: invalid operands `subu\.e \$4,\$16,4' -.*:19: Error: invalid operands `subu\.e \$5,\$17,16384' +.*:14: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$2,-32767' +.*:15: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,16' +.*:16: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,32768' +.*:17: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,\$7,-16383' +.*:18: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,\$16,4' +.*:19: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$5,\$17,16384' .*:20: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu\.e \$4,-32767' .*:21: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu\.e \$6,6' .*:22: Error: opcode not supported on this processor: mips1 \(mips1\) `dsubu\.e \$7,32768' diff --git a/gas/testsuite/gas/mips/mips16-64@mips16-insn-e.d b/gas/testsuite/gas/mips/mips16-64@mips16-insn-e.d new file mode 100644 index 0000000..7b1814d --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-64@mips16-insn-e.d @@ -0,0 +1,4 @@ +#as: -32 +#name: MIPS16 explicit extended instructions +#error-output: mips16-64@mips16-insn-e.l +#source: mips16-insn-e.s diff --git a/gas/testsuite/gas/mips/mips16-64@mips16-insn-e.l b/gas/testsuite/gas/mips/mips16-64@mips16-insn-e.l new file mode 100644 index 0000000..3cf4de7 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-64@mips16-insn-e.l @@ -0,0 +1,132 @@ +.*: Assembler messages: +.*:4: Warning: extended operand requested but not required +.*:5: Warning: extended operand requested but not required +.*:8: Warning: extended operand requested but not required +.*:9: Warning: extended operand requested but not required +.*:23: Warning: extended operand requested but not required +.*:24: Warning: extended operand requested but not required +.*:25: Warning: extended operand requested but not required +.*:26: Warning: extended operand requested but not required +.*:28: Warning: extended operand requested but not required +.*:30: Warning: extended operand requested but not required +.*:31: Warning: extended operand requested but not required +.*:32: Warning: extended operand requested but not required +.*:33: Warning: extended operand requested but not required +.*:35: Warning: extended operand requested but not required +.*:36: Warning: extended operand requested but not required +.*:38: Warning: extended operand requested but not required +.*:39: Warning: extended operand requested but not required +.*:41: Warning: extended operand requested but not required +.*:42: Warning: extended operand requested but not required +.*:46: Warning: extended operand requested but not required +.*:47: Warning: extended operand requested but not required +.*:48: Warning: extended operand requested but not required +.*:49: Warning: extended operand requested but not required +.*:50: Warning: extended operand requested but not required +.*:51: Error: opcode not supported on this processor: mips3 \(mips3\) `restore\.e 128' +.*:52: Error: opcode not supported on this processor: mips3 \(mips3\) `save\.e 128' +.*:53: Error: unrecognized extended version of MIPS16 opcode `nop\.e ' +.*:54: Error: unrecognized extended version of MIPS16 opcode `move\.e \$0,\$16' +.*:55: Error: unrecognized extended version of MIPS16 opcode `move\.e \$16,\$0' +.*:57: Warning: extended operand requested but not required +.*:59: Warning: extended operand requested but not required +.*:60: Warning: extended operand requested but not required +.*:62: Warning: extended operand requested but not required +.*:64: Warning: extended operand requested but not required +.*:66: Warning: extended operand requested but not required +.*:68: Warning: extended operand requested but not required +.*:70: Warning: extended operand requested but not required +.*:72: Warning: extended operand requested but not required +.*:74: Warning: extended operand requested but not required +.*:77: Warning: extended operand requested but not required +.*:80: Warning: extended operand requested but not required +.*:82: Warning: extended operand requested but not required +.*:84: Warning: extended operand requested but not required +.*:86: Warning: extended operand requested but not required +.*:88: Warning: extended operand requested but not required +.*:90: Error: invalid operands `daddu\.e \$16,\$16,\$16' +.*:91: Error: invalid operands `addu\.e \$16,\$16,\$16' +.*:92: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$16,\$16,\$16' +.*:93: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$16,\$16,\$16' +.*:95: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$16' +.*:97: Error: unrecognized extended version of MIPS16 opcode `j\.e \$16' +.*:99: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$31' +.*:101: Error: unrecognized extended version of MIPS16 opcode `j\.e \$31' +.*:103: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$16' +.*:105: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$31,\$16' +.*:107: Error: operand 1 must be an immediate expression `jal\.e \$16' +.*:109: Error: operand 1 must be an immediate expression `jal\.e \$31,\$16' +.*:111: Error: opcode not supported on this processor: mips3 \(mips3\) `jrc\.e \$16' +.*:112: Error: opcode not supported on this processor: mips3 \(mips3\) `jrc\.e \$31' +.*:113: Error: opcode not supported on this processor: mips3 \(mips3\) `jalrc\.e \$16' +.*:114: Error: opcode not supported on this processor: mips3 \(mips3\) `jalrc\.e \$31,\$16' +.*:115: Error: opcode not supported on this processor: mips3 \(mips3\) `sdbbp\.e 0' +.*:116: Error: invalid operands `slt\.e \$16,\$16' +.*:117: Error: invalid operands `sltu\.e \$16,\$16' +.*:118: Error: unrecognized extended version of MIPS16 opcode `sllv\.e \$16,\$16' +.*:119: Error: invalid operands `sll\.e \$16,\$16' +.*:120: Error: unrecognized extended version of MIPS16 opcode `break\.e 0' +.*:121: Error: unrecognized extended version of MIPS16 opcode `srlv\.e \$16,\$16' +.*:122: Error: invalid operands `srl\.e \$16,\$16' +.*:123: Error: unrecognized extended version of MIPS16 opcode `srav\.e \$16,\$16' +.*:124: Error: invalid operands `sra\.e \$16,\$16' +.*:125: Warning: extended operand requested but not required +.*:126: Error: unrecognized extended version of MIPS16 opcode `entry\.e ' +.*:127: Error: unrecognized extended version of MIPS16 opcode `entry\.e \$31' +.*:128: Error: unrecognized extended version of MIPS16 opcode `exit\.e \$f0' +.*:129: Error: unrecognized extended version of MIPS16 opcode `exit\.e' +.*:130: Error: invalid operands `cmp\.e \$16,\$16' +.*:131: Error: unrecognized extended version of MIPS16 opcode `neg\.e \$16,\$16' +.*:132: Error: unrecognized extended version of MIPS16 opcode `and\.e \$16,\$16' +.*:133: Error: unrecognized extended version of MIPS16 opcode `or\.e \$16,\$16' +.*:134: Error: unrecognized extended version of MIPS16 opcode `xor\.e \$16,\$16' +.*:135: Error: unrecognized extended version of MIPS16 opcode `not\.e \$16,\$16' +.*:136: Error: unrecognized extended version of MIPS16 opcode `mfhi\.e \$16' +.*:137: Error: opcode not supported on this processor: mips3 \(mips3\) `zeb\.e \$16' +.*:138: Error: opcode not supported on this processor: mips3 \(mips3\) `zeh\.e \$16' +.*:139: Error: opcode not supported on this processor: mips3 \(mips3\) `zew\.e \$16' +.*:140: Error: opcode not supported on this processor: mips3 \(mips3\) `seb\.e \$16' +.*:141: Error: opcode not supported on this processor: mips3 \(mips3\) `seh\.e \$16' +.*:142: Error: opcode not supported on this processor: mips3 \(mips3\) `sew\.e \$16' +.*:143: Error: unrecognized extended version of MIPS16 opcode `mflo\.e \$16' +.*:144: Warning: extended operand requested but not required +.*:145: Error: unrecognized extended version of MIPS16 opcode `dsllv\.e \$16,\$16' +.*:146: Error: invalid operands `dsll\.e \$16,\$16' +.*:147: Error: unrecognized extended version of MIPS16 opcode `dsrlv\.e \$16,\$16' +.*:148: Error: invalid operands `dsrl\.e \$16,\$16' +.*:149: Error: unrecognized extended version of MIPS16 opcode `dsrav\.e \$16,\$16' +.*:150: Error: invalid operands `dsra\.e \$16,\$16' +.*:151: Error: unrecognized extended version of MIPS16 opcode `mult\.e \$16,\$16' +.*:152: Error: unrecognized extended version of MIPS16 opcode `multu\.e \$16,\$16' +.*:153: Error: unrecognized extended version of MIPS16 opcode `div\.e \$0,\$16,\$16' +.*:154: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$0,\$16,\$16' +.*:155: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$0,\$16,\$16' +.*:156: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$0,\$16,\$16' +.*:157: Error: unrecognized extended version of MIPS16 opcode `dmult\.e \$16,\$16' +.*:158: Error: unrecognized extended version of MIPS16 opcode `dmultu\.e \$16,\$16' +.*:159: Error: unrecognized extended version of MIPS16 opcode `ddiv\.e \$0,\$16,\$16' +.*:160: Error: unrecognized extended version of MIPS16 opcode `drem\.e \$0,\$16,\$16' +.*:161: Error: unrecognized extended version of MIPS16 opcode `ddivu\.e \$0,\$16,\$16' +.*:162: Error: unrecognized extended version of MIPS16 opcode `dremu\.e \$0,\$16,\$16' +.*:164: Error: unrecognized extended version of MIPS16 opcode `extend\.e 0' +.*:166: Warning: extended operand requested but not required +.*:167: Warning: extended operand requested but not required +.*:168: Warning: extended operand requested but not required +.*:169: Warning: extended operand requested but not required +.*:170: Warning: extended operand requested but not required +.*:171: Warning: extended operand requested but not required +.*:172: Warning: extended operand requested but not required +.*:174: Warning: extended operand requested but not required +.*:176: Warning: extended operand requested but not required +.*:177: Warning: extended operand requested but not required +.*:179: Warning: extended operand requested but not required +.*:180: Warning: extended operand requested but not required +.*:182: Warning: extended operand requested but not required +.*:183: Warning: extended operand requested but not required +.*:10: Warning: extended operand requested but not required +.*:12: Warning: extended operand requested but not required +.*:19: Warning: extended operand requested but not required +.*:21: Warning: extended operand requested but not required +.*:44: Warning: extended operand requested but not required +.*:45: Warning: extended operand requested but not required +.*:181: Warning: extended operand requested but not required diff --git a/gas/testsuite/gas/mips/mips16-64@mips16-insn-t.d b/gas/testsuite/gas/mips/mips16-64@mips16-insn-t.d new file mode 100644 index 0000000..57ea2be --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-64@mips16-insn-t.d @@ -0,0 +1,4 @@ +#as: -32 +#name: MIPS16 explicit unextended instructions +#error-output: mips16-64@mips16-insn-t.l +#source: mips16-insn-t.s diff --git a/gas/testsuite/gas/mips/mips16-64@mips16-insn-t.l b/gas/testsuite/gas/mips/mips16-64@mips16-insn-t.l new file mode 100644 index 0000000..3f9c578 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-64@mips16-insn-t.l @@ -0,0 +1,16 @@ +.*: Assembler messages: +.*:14: Error: invalid operands `jal\.t 0' +.*:16: Error: unrecognized unextended version of MIPS16 opcode `jalx\.t 0' +.*:51: Error: opcode not supported on this processor: mips3 \(mips3\) `restore\.t 128' +.*:52: Error: opcode not supported on this processor: mips3 \(mips3\) `save\.t 128' +.*:111: Error: opcode not supported on this processor: mips3 \(mips3\) `jrc\.t \$16' +.*:112: Error: opcode not supported on this processor: mips3 \(mips3\) `jrc\.t \$31' +.*:113: Error: opcode not supported on this processor: mips3 \(mips3\) `jalrc\.t \$16' +.*:114: Error: opcode not supported on this processor: mips3 \(mips3\) `jalrc\.t \$31,\$16' +.*:115: Error: opcode not supported on this processor: mips3 \(mips3\) `sdbbp\.t 0' +.*:137: Error: opcode not supported on this processor: mips3 \(mips3\) `zeb\.t \$16' +.*:138: Error: opcode not supported on this processor: mips3 \(mips3\) `zeh\.t \$16' +.*:139: Error: opcode not supported on this processor: mips3 \(mips3\) `zew\.t \$16' +.*:140: Error: opcode not supported on this processor: mips3 \(mips3\) `seb\.t \$16' +.*:141: Error: opcode not supported on this processor: mips3 \(mips3\) `seh\.t \$16' +.*:142: Error: opcode not supported on this processor: mips3 \(mips3\) `sew\.t \$16' diff --git a/gas/testsuite/gas/mips/mips16-extend-swap.d b/gas/testsuite/gas/mips/mips16-extend-swap.d index eb9dd73..d60ab7f 100644 --- a/gas/testsuite/gas/mips/mips16-extend-swap.d +++ b/gas/testsuite/gas/mips/mips16-extend-swap.d @@ -13,10 +13,13 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f123 extend 0x123 [0-9a-f]+ <[^>]*> 1c00 0000 jalx 00000000 <foo> [0-9a-f]+ <[^>]*> 6500 nop -[0-9a-f]+ <[^>]*> f123 eb00 jr v1 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> eb00 jr v1 [0-9a-f]+ <[^>]*> 6500 nop -[0-9a-f]+ <[^>]*> f123 e820 jr ra +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> e820 jr ra [0-9a-f]+ <[^>]*> 6500 nop -[0-9a-f]+ <[^>]*> f123 eb40 jalr v1 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> eb40 jalr v1 [0-9a-f]+ <[^>]*> 6500 nop \.\.\. diff --git a/gas/testsuite/gas/mips/mips16-insn-e.d b/gas/testsuite/gas/mips/mips16-insn-e.d new file mode 100644 index 0000000..5a28fea --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-insn-e.d @@ -0,0 +1,3 @@ +#as: -32 +#name: MIPS16 explicit extended instructions +#error-output: mips16-insn-e.l diff --git a/gas/testsuite/gas/mips/mips16-insn-e.l b/gas/testsuite/gas/mips/mips16-insn-e.l new file mode 100644 index 0000000..3ac944e --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-insn-e.l @@ -0,0 +1,130 @@ +.*: Assembler messages: +.*:4: Warning: extended operand requested but not required +.*:5: Warning: extended operand requested but not required +.*:8: Warning: extended operand requested but not required +.*:9: Warning: extended operand requested but not required +.*:23: Warning: extended operand requested but not required +.*:24: Warning: extended operand requested but not required +.*:25: Warning: extended operand requested but not required +.*:26: Warning: extended operand requested but not required +.*:28: Warning: extended operand requested but not required +.*:30: Warning: extended operand requested but not required +.*:31: Warning: extended operand requested but not required +.*:32: Warning: extended operand requested but not required +.*:33: Warning: extended operand requested but not required +.*:35: Warning: extended operand requested but not required +.*:36: Warning: extended operand requested but not required +.*:38: Warning: extended operand requested but not required +.*:39: Warning: extended operand requested but not required +.*:41: Warning: extended operand requested but not required +.*:42: Warning: extended operand requested but not required +.*:46: Warning: extended operand requested but not required +.*:47: Warning: extended operand requested but not required +.*:48: Warning: extended operand requested but not required +.*:49: Warning: extended operand requested but not required +.*:50: Warning: extended operand requested but not required +.*:53: Error: unrecognized extended version of MIPS16 opcode `nop\.e ' +.*:54: Error: unrecognized extended version of MIPS16 opcode `move\.e \$0,\$16' +.*:55: Error: unrecognized extended version of MIPS16 opcode `move\.e \$16,\$0' +.*:57: Warning: extended operand requested but not required +.*:59: Warning: extended operand requested but not required +.*:60: Warning: extended operand requested but not required +.*:62: Warning: extended operand requested but not required +.*:64: Warning: extended operand requested but not required +.*:66: Warning: extended operand requested but not required +.*:68: Warning: extended operand requested but not required +.*:70: Warning: extended operand requested but not required +.*:72: Warning: extended operand requested but not required +.*:74: Warning: extended operand requested but not required +.*:77: Warning: extended operand requested but not required +.*:80: Warning: extended operand requested but not required +.*:82: Warning: extended operand requested but not required +.*:84: Warning: extended operand requested but not required +.*:86: Warning: extended operand requested but not required +.*:88: Warning: extended operand requested but not required +.*:90: Error: invalid operands `daddu\.e \$16,\$16,\$16' +.*:91: Error: invalid operands `addu\.e \$16,\$16,\$16' +.*:92: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$16,\$16,\$16' +.*:93: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$16,\$16,\$16' +.*:95: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$16' +.*:97: Error: unrecognized extended version of MIPS16 opcode `j\.e \$16' +.*:99: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$31' +.*:101: Error: unrecognized extended version of MIPS16 opcode `j\.e \$31' +.*:103: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$16' +.*:105: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$31,\$16' +.*:107: Error: operand 1 must be an immediate expression `jal\.e \$16' +.*:109: Error: operand 1 must be an immediate expression `jal\.e \$31,\$16' +.*:111: Error: unrecognized extended version of MIPS16 opcode `jrc\.e \$16' +.*:112: Error: unrecognized extended version of MIPS16 opcode `jrc\.e \$31' +.*:113: Error: unrecognized extended version of MIPS16 opcode `jalrc\.e \$16' +.*:114: Error: unrecognized extended version of MIPS16 opcode `jalrc\.e \$31,\$16' +.*:115: Error: unrecognized extended version of MIPS16 opcode `sdbbp\.e 0' +.*:116: Error: invalid operands `slt\.e \$16,\$16' +.*:117: Error: invalid operands `sltu\.e \$16,\$16' +.*:118: Error: unrecognized extended version of MIPS16 opcode `sllv\.e \$16,\$16' +.*:119: Error: invalid operands `sll\.e \$16,\$16' +.*:120: Error: unrecognized extended version of MIPS16 opcode `break\.e 0' +.*:121: Error: unrecognized extended version of MIPS16 opcode `srlv\.e \$16,\$16' +.*:122: Error: invalid operands `srl\.e \$16,\$16' +.*:123: Error: unrecognized extended version of MIPS16 opcode `srav\.e \$16,\$16' +.*:124: Error: invalid operands `sra\.e \$16,\$16' +.*:125: Warning: extended operand requested but not required +.*:126: Error: unrecognized extended version of MIPS16 opcode `entry\.e ' +.*:127: Error: unrecognized extended version of MIPS16 opcode `entry\.e \$31' +.*:128: Error: unrecognized extended version of MIPS16 opcode `exit\.e \$f0' +.*:129: Error: unrecognized extended version of MIPS16 opcode `exit\.e' +.*:130: Error: invalid operands `cmp\.e \$16,\$16' +.*:131: Error: unrecognized extended version of MIPS16 opcode `neg\.e \$16,\$16' +.*:132: Error: unrecognized extended version of MIPS16 opcode `and\.e \$16,\$16' +.*:133: Error: unrecognized extended version of MIPS16 opcode `or\.e \$16,\$16' +.*:134: Error: unrecognized extended version of MIPS16 opcode `xor\.e \$16,\$16' +.*:135: Error: unrecognized extended version of MIPS16 opcode `not\.e \$16,\$16' +.*:136: Error: unrecognized extended version of MIPS16 opcode `mfhi\.e \$16' +.*:137: Error: unrecognized extended version of MIPS16 opcode `zeb\.e \$16' +.*:138: Error: unrecognized extended version of MIPS16 opcode `zeh\.e \$16' +.*:139: Error: unrecognized extended version of MIPS16 opcode `zew\.e \$16' +.*:140: Error: unrecognized extended version of MIPS16 opcode `seb\.e \$16' +.*:141: Error: unrecognized extended version of MIPS16 opcode `seh\.e \$16' +.*:142: Error: unrecognized extended version of MIPS16 opcode `sew\.e \$16' +.*:143: Error: unrecognized extended version of MIPS16 opcode `mflo\.e \$16' +.*:144: Warning: extended operand requested but not required +.*:145: Error: unrecognized extended version of MIPS16 opcode `dsllv\.e \$16,\$16' +.*:146: Error: invalid operands `dsll\.e \$16,\$16' +.*:147: Error: unrecognized extended version of MIPS16 opcode `dsrlv\.e \$16,\$16' +.*:148: Error: invalid operands `dsrl\.e \$16,\$16' +.*:149: Error: unrecognized extended version of MIPS16 opcode `dsrav\.e \$16,\$16' +.*:150: Error: invalid operands `dsra\.e \$16,\$16' +.*:151: Error: unrecognized extended version of MIPS16 opcode `mult\.e \$16,\$16' +.*:152: Error: unrecognized extended version of MIPS16 opcode `multu\.e \$16,\$16' +.*:153: Error: unrecognized extended version of MIPS16 opcode `div\.e \$0,\$16,\$16' +.*:154: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$0,\$16,\$16' +.*:155: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$0,\$16,\$16' +.*:156: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$0,\$16,\$16' +.*:157: Error: unrecognized extended version of MIPS16 opcode `dmult\.e \$16,\$16' +.*:158: Error: unrecognized extended version of MIPS16 opcode `dmultu\.e \$16,\$16' +.*:159: Error: unrecognized extended version of MIPS16 opcode `ddiv\.e \$0,\$16,\$16' +.*:160: Error: unrecognized extended version of MIPS16 opcode `drem\.e \$0,\$16,\$16' +.*:161: Error: unrecognized extended version of MIPS16 opcode `ddivu\.e \$0,\$16,\$16' +.*:162: Error: unrecognized extended version of MIPS16 opcode `dremu\.e \$0,\$16,\$16' +.*:164: Error: unrecognized extended version of MIPS16 opcode `extend\.e 0' +.*:166: Warning: extended operand requested but not required +.*:167: Warning: extended operand requested but not required +.*:168: Warning: extended operand requested but not required +.*:169: Warning: extended operand requested but not required +.*:170: Warning: extended operand requested but not required +.*:171: Warning: extended operand requested but not required +.*:172: Warning: extended operand requested but not required +.*:174: Warning: extended operand requested but not required +.*:176: Warning: extended operand requested but not required +.*:177: Warning: extended operand requested but not required +.*:179: Warning: extended operand requested but not required +.*:180: Warning: extended operand requested but not required +.*:182: Warning: extended operand requested but not required +.*:183: Warning: extended operand requested but not required +.*:10: Warning: extended operand requested but not required +.*:12: Warning: extended operand requested but not required +.*:19: Warning: extended operand requested but not required +.*:21: Warning: extended operand requested but not required +.*:44: Warning: extended operand requested but not required +.*:45: Warning: extended operand requested but not required +.*:181: Warning: extended operand requested but not required diff --git a/gas/testsuite/gas/mips/mips16-insn-e.s b/gas/testsuite/gas/mips/mips16-insn-e.s new file mode 100644 index 0000000..b175cd1 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-insn-e.s @@ -0,0 +1,187 @@ + .set mips16 + .set noreorder +foo: + addiu.e $16, $29, 0 # ADDIUSP + addu.e $16, $29, 0 + + .align 2 + addiu.e $16, $pc, 0 # ADDIUPC + addu.e $16, $pc, 0 + la.e $16, . - 1 + + b.e . + 2 # B + + jal.e 0 # JAL(X) + nop + jalx.e 0 + nop + + beqz.e $16, . + 2 # BEQZ + + bnez.e $16, . + 2 # BNEZ + + sll.e $16, $16, 8 # SHIFT # SLL + dsll.e $16, $16, 8 # DSLL + srl.e $16, $16, 8 # SRL + sra.e $16, $16, 8 # SRA + + ld.e $16, 0($16) # LD + + addiu.e $16, $16, 0 # RRI-A # ADDIU + addu.e $16, $16, 0 + daddiu.e $16, $16, 0 # DADDIU + daddu.e $16, $16, 0 + + addiu.e $16, 0 # ADDIU8 + addu.e $16, 0 + + slti.e $16, 0 # SLTI + slt.e $16, 0 + + sltiu.e $16, 0 # SLTIU + sltu.e $16, 0 + + bteqz.e . + 2 # I8 # BTEQZ + btnez.e . + 2 # BTNEZ + sw.e $31, 0($29) # SWRASP + addiu.e $29, 0 # ADJSP + addiu.e $29, $29, 0 + addu.e $29, 0 + addu.e $29, $29, 0 + restore.e 128 # SVRS # RESTORE + save.e 128 # SAVE + nop.e # MOV32R + move.e $0, $16 + move.e $16, $0 # MOVR32 + + li.e $16, 0 # LI + + cmpi.e $16, 0 # CMPI + cmp.e $16, 0 + + sd.e $16, 0($16) # SD + + lb.e $16, 0($16) # LB + + lh.e $16, 0($16) # LH + + lw.e $16, 0($29) # LWSP + + lw.e $16, 0($16) # LW + + lbu.e $16, 0($16) # LBU + + lhu.e $16, 0($16) # LHU + + .align 2 + lw.e $16, 0($pc) # LWPC + lw.e $16, . - 3 + + lwu.e $16, 0($16) # LWU + + sb.e $16, 0($16) # SB + + sh.e $16, 0($16) # SH + + sw.e $16, 0($29) # SWSP + + sw.e $16, 0($16) # SW + + daddu.e $16, $16, $16 # RRR # DADDU + addu.e $16, $16, $16 # ADDU + dsubu.e $16, $16, $16 # DSUBU + subu.e $16, $16, $16 # SUBU + + jr.e $16 # RR # J(AL)R(C) # JR rx + nop + j.e $16 + nop + jr.e $31 # JR ra + nop + j.e $31 + nop + jalr.e $16 # JALR + nop + jalr.e $31, $16 + nop + jal.e $16 + nop + jal.e $31, $16 + nop + jrc.e $16 # JRC rx + jrc.e $31 # JRC ra + jalrc.e $16 # JALRC + jalrc.e $31, $16 + sdbbp.e 0 # SDBBP + slt.e $16, $16 # SLT + sltu.e $16, $16 # SLTU + sllv.e $16, $16 # SLLV + sll.e $16, $16 + break.e 0 # BREAK + srlv.e $16, $16 # SRLV + srl.e $16, $16 + srav.e $16, $16 # SRAV + sra.e $16, $16 + dsrl.e $16, 8 # DSRL + entry.e # ENTRY/EXIT + entry.e $31 + exit.e $f0 + exit.e + cmp.e $16, $16 # CMP + neg.e $16, $16 # NEG + and.e $16, $16 # AND + or.e $16, $16 # OR + xor.e $16, $16 # XOR + not.e $16, $16 # NOT + mfhi.e $16 # MFHI + zeb.e $16 # CNVT # ZEB + zeh.e $16 # ZEH + zew.e $16 # ZEW + seb.e $16 # SEB + seh.e $16 # SEH + sew.e $16 # SEW + mflo.e $16 # MFLO + dsra.e $16, 8 # DSRA + dsllv.e $16, $16 # DSLLV + dsll.e $16, $16 + dsrlv.e $16, $16 # DSRLV + dsrl.e $16, $16 + dsrav.e $16, $16 # DSRAV + dsra.e $16, $16 + mult.e $16, $16 # MULT + multu.e $16, $16 # MULTU + div.e $0, $16, $16 # DIV + rem.e $0, $16, $16 + divu.e $0, $16, $16 # DIVU + remu.e $0, $16, $16 + dmult.e $16, $16 # DMULT + dmultu.e $16, $16 # DMULTU + ddiv.e $0, $16, $16 # DDIV + drem.e $0, $16, $16 + ddivu.e $0, $16, $16 # DDIVU + dremu.e $0, $16, $16 + + extend.e 0 # EXTEND + + ld.e $16, 0($29) # I64 # LDSP + sd.e $16, 0($29) # SDSP + sd.e $31, 0($29) # SDRASP + daddiu.e $29, 0 # DADJSP + daddiu.e $29, $29, 0 + daddu.e $29, 0 + daddu.e $29, $29, 0 + .align 3 + ld.e $16, 0($pc) # LDPC + ld.e $16, . - 3 + daddiu.e $16, 0 # DADDIU5 + daddu.e $16, 0 + .align 2 + daddiu.e $16, $pc, 0 # DADDIUPC + daddu.e $16, $pc, 0 + dla.e $16, . - 1 + daddiu.e $16, $sp, 0 # DADDIUSP + daddu.e $16, $sp, 0 + +# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 4, 0 + .space 16 diff --git a/gas/testsuite/gas/mips/mips16-insn-t.d b/gas/testsuite/gas/mips/mips16-insn-t.d new file mode 100644 index 0000000..a0b7e64 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-insn-t.d @@ -0,0 +1,3 @@ +#as: -32 +#name: MIPS16 explicit unextended instructions +#error-output: mips16-insn-t.l diff --git a/gas/testsuite/gas/mips/mips16-insn-t.l b/gas/testsuite/gas/mips/mips16-insn-t.l new file mode 100644 index 0000000..c15c066 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-insn-t.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:14: Error: invalid operands `jal\.t 0' +.*:16: Error: unrecognized unextended version of MIPS16 opcode `jalx\.t 0' diff --git a/gas/testsuite/gas/mips/mips16-insn-t.s b/gas/testsuite/gas/mips/mips16-insn-t.s new file mode 100644 index 0000000..6e2d86d --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-insn-t.s @@ -0,0 +1,187 @@ + .set mips16 + .set noreorder +foo: + addiu.t $16, $29, 0 # ADDIUSP + addu.t $16, $29, 0 + + .align 2 + addiu.t $16, $pc, 0 # ADDIUPC + addu.t $16, $pc, 0 + la.t $16, . - 1 + + b.t . + 2 # B + + jal.t 0 # JAL(X) + nop + jalx.t 0 + nop + + beqz.t $16, . + 2 # BEQZ + + bnez.t $16, . + 2 # BNEZ + + sll.t $16, $16, 8 # SHIFT # SLL + dsll.t $16, $16, 8 # DSLL + srl.t $16, $16, 8 # SRL + sra.t $16, $16, 8 # SRA + + ld.t $16, 0($16) # LD + + addiu.t $16, $16, 0 # RRI-A # ADDIU + addu.t $16, $16, 0 + daddiu.t $16, $16, 0 # DADDIU + daddu.t $16, $16, 0 + + addiu.t $16, 0 # ADDIU8 + addu.t $16, 0 + + slti.t $16, 0 # SLTI + slt.t $16, 0 + + sltiu.t $16, 0 # SLTIU + sltu.t $16, 0 + + bteqz.t . + 2 # I8 # BTEQZ + btnez.t . + 2 # BTNEZ + sw.t $31, 0($29) # SWRASP + addiu.t $29, 0 # ADJSP + addiu.t $29, $29, 0 + addu.t $29, 0 + addu.t $29, $29, 0 + restore.t 128 # SVRS # RESTORE + save.t 128 # SAVE + nop.t # MOV32R + move.t $0, $16 + move.t $16, $0 # MOVR32 + + li.t $16, 0 # LI + + cmpi.t $16, 0 # CMPI + cmp.t $16, 0 + + sd.t $16, 0($16) # SD + + lb.t $16, 0($16) # LB + + lh.t $16, 0($16) # LH + + lw.t $16, 0($29) # LWSP + + lw.t $16, 0($16) # LW + + lbu.t $16, 0($16) # LBU + + lhu.t $16, 0($16) # LHU + + .align 2 + lw.t $16, 0($pc) # LWPC + lw.t $16, . - 3 + + lwu.t $16, 0($16) # LWU + + sb.t $16, 0($16) # SB + + sh.t $16, 0($16) # SH + + sw.t $16, 0($29) # SWSP + + sw.t $16, 0($16) # SW + + daddu.t $16, $16, $16 # RRR # DADDU + addu.t $16, $16, $16 # ADDU + dsubu.t $16, $16, $16 # DSUBU + subu.t $16, $16, $16 # SUBU + + jr.t $16 # RR # J(AL)R(C) # JR rx + nop + j.t $16 + nop + jr.t $31 # JR ra + nop + j.t $31 + nop + jalr.t $16 # JALR + nop + jalr.t $31, $16 + nop + jal.t $16 + nop + jal.t $31, $16 + nop + jrc.t $16 # JRC rx + jrc.t $31 # JRC ra + jalrc.t $16 # JALRC + jalrc.t $31, $16 + sdbbp.t 0 # SDBBP + slt.t $16, $16 # SLT + sltu.t $16, $16 # SLTU + sllv.t $16, $16 # SLLV + sll.t $16, $16 + break.t 0 # BREAK + srlv.t $16, $16 # SRLV + srl.t $16, $16 + srav.t $16, $16 # SRAV + sra.t $16, $16 + dsrl.t $16, 8 # DSRL + entry.t # ENTRY/EXIT + entry.t $31 + exit.t $f0 + exit.t + cmp.t $16, $16 # CMP + neg.t $16, $16 # NEG + and.t $16, $16 # AND + or.t $16, $16 # OR + xor.t $16, $16 # XOR + not.t $16, $16 # NOT + mfhi.t $16 # MFHI + zeb.t $16 # CNVT # ZEB + zeh.t $16 # ZEH + zew.t $16 # ZEW + seb.t $16 # SEB + seh.t $16 # SEH + sew.t $16 # SEW + mflo.t $16 # MFLO + dsra.t $16, 8 # DSRA + dsllv.t $16, $16 # DSLLV + dsll.t $16, $16 + dsrlv.t $16, $16 # DSRLV + dsrl.t $16, $16 + dsrav.t $16, $16 # DSRAV + dsra.t $16, $16 + mult.t $16, $16 # MULT + multu.t $16, $16 # MULTU + div.t $0, $16, $16 # DIV + rem.t $0, $16, $16 + divu.t $0, $16, $16 # DIVU + remu.t $0, $16, $16 + dmult.t $16, $16 # DMULT + dmultu.t $16, $16 # DMULTU + ddiv.t $0, $16, $16 # DDIV + drem.t $0, $16, $16 + ddivu.t $0, $16, $16 # DDIVU + dremu.t $0, $16, $16 + + extend.t 0 # EXTEND + + ld.t $16, 0($29) # I64 # LDSP + sd.t $16, 0($29) # SDSP + sd.t $31, 0($29) # SDRASP + daddiu.t $29, 0 # DADJSP + daddiu.t $29, $29, 0 + daddu.t $29, 0 + daddu.t $29, $29, 0 + .align 3 + ld.t $16, 0($pc) # LDPC + ld.t $16, . - 3 + daddiu.t $16, 0 # DADDIU5 + daddu.t $16, 0 + .align 2 + daddiu.t $16, $pc, 0 # DADDIUPC + daddu.t $16, $pc, 0 + dla.t $16, . - 1 + daddiu.t $16, $sp, 0 # DADDIUSP + daddu.t $16, $sp, 0 + +# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 4, 0 + .space 16 diff --git a/gas/testsuite/gas/mips/mips16-macro-e.l b/gas/testsuite/gas/mips/mips16-macro-e.l index 225d9a9..663d87b 100644 --- a/gas/testsuite/gas/mips/mips16-macro-e.l +++ b/gas/testsuite/gas/mips/mips16-macro-e.l @@ -1,26 +1,26 @@ .*: Assembler messages: -.*:4: Error: invalid operands `div\.e \$2,\$3,\$4' -.*:5: Error: invalid operands `divu\.e \$3,\$4,\$5' -.*:6: Error: invalid operands `ddiv\.e \$4,\$5,\$6' -.*:7: Error: invalid operands `ddivu\.e \$5,\$6,\$7' -.*:8: Error: invalid operands `rem\.e \$6,\$7,\$16' -.*:9: Error: invalid operands `remu\.e \$6,\$7,\$17' -.*:10: Error: invalid operands `drem\.e \$2,\$3,\$4' -.*:11: Error: invalid operands `dremu\.e \$3,\$4,\$5' +.*:4: Error: unrecognized extended version of MIPS16 opcode `div\.e \$2,\$3,\$4' +.*:5: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$3,\$4,\$5' +.*:6: Error: unrecognized extended version of MIPS16 opcode `ddiv\.e \$4,\$5,\$6' +.*:7: Error: unrecognized extended version of MIPS16 opcode `ddivu\.e \$5,\$6,\$7' +.*:8: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$6,\$7,\$16' +.*:9: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$6,\$7,\$17' +.*:10: Error: unrecognized extended version of MIPS16 opcode `drem\.e \$2,\$3,\$4' +.*:11: Error: unrecognized extended version of MIPS16 opcode `dremu\.e \$3,\$4,\$5' .*:12: Error: unrecognized extended version of MIPS16 opcode `mul\.e \$4,\$5,\$6' .*:13: Error: unrecognized extended version of MIPS16 opcode `dmul\.e \$5,\$6,\$7' -.*:14: Error: invalid operands `subu\.e \$2,-32767' -.*:15: Error: invalid operands `subu\.e \$3,16' -.*:16: Error: invalid operands `subu\.e \$4,32768' -.*:17: Error: invalid operands `subu\.e \$3,\$7,-16383' -.*:18: Error: invalid operands `subu\.e \$4,\$16,4' -.*:19: Error: invalid operands `subu\.e \$5,\$17,16384' -.*:20: Error: invalid operands `dsubu\.e \$4,-32767' -.*:21: Error: invalid operands `dsubu\.e \$6,6' -.*:22: Error: invalid operands `dsubu\.e \$7,32768' -.*:23: Error: invalid operands `dsubu\.e \$2,\$4,-16383' -.*:24: Error: invalid operands `dsubu\.e \$3,\$7,8' -.*:25: Error: invalid operands `dsubu\.e \$4,\$5,16384' +.*:14: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$2,-32767' +.*:15: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,16' +.*:16: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,32768' +.*:17: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,\$7,-16383' +.*:18: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,\$16,4' +.*:19: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$5,\$17,16384' +.*:20: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$4,-32767' +.*:21: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$6,6' +.*:22: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$7,32768' +.*:23: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$2,\$4,-16383' +.*:24: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$3,\$7,8' +.*:25: Error: unrecognized extended version of MIPS16 opcode `dsubu\.e \$4,\$5,16384' .*:26: Error: unrecognized extended version of MIPS16 opcode `beq\.e \$2,\$3,1b' .*:27: Error: unrecognized extended version of MIPS16 opcode `bne\.e \$4,\$5,1b' .*:28: Error: unrecognized extended version of MIPS16 opcode `blt\.e \$6,\$7,1b' diff --git a/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.d b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.d new file mode 100644 index 0000000..1f5edee --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.d @@ -0,0 +1,4 @@ +#as: -32 +#name: MIPS16 explicit extended instructions +#error-output: mips16e-32@mips16-insn-e.l +#source: mips16-insn-e.s diff --git a/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.l b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.l new file mode 100644 index 0000000..2c53785 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-e.l @@ -0,0 +1,131 @@ +.*: Assembler messages: +.*:4: Warning: extended operand requested but not required +.*:5: Warning: extended operand requested but not required +.*:8: Warning: extended operand requested but not required +.*:9: Warning: extended operand requested but not required +.*:23: Warning: extended operand requested but not required +.*:24: Error: opcode not supported on this processor: mips32 \(mips32\) `dsll\.e \$16,\$16,8' +.*:25: Warning: extended operand requested but not required +.*:26: Warning: extended operand requested but not required +.*:28: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.e \$16,0\(\$16\)' +.*:30: Warning: extended operand requested but not required +.*:31: Warning: extended operand requested but not required +.*:32: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$16,\$16,0' +.*:33: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,\$16,0' +.*:35: Warning: extended operand requested but not required +.*:36: Warning: extended operand requested but not required +.*:38: Warning: extended operand requested but not required +.*:39: Warning: extended operand requested but not required +.*:41: Warning: extended operand requested but not required +.*:42: Warning: extended operand requested but not required +.*:46: Warning: extended operand requested but not required +.*:47: Warning: extended operand requested but not required +.*:48: Warning: extended operand requested but not required +.*:49: Warning: extended operand requested but not required +.*:50: Warning: extended operand requested but not required +.*:53: Error: unrecognized extended version of MIPS16 opcode `nop\.e ' +.*:54: Error: unrecognized extended version of MIPS16 opcode `move\.e \$0,\$16' +.*:55: Error: unrecognized extended version of MIPS16 opcode `move\.e \$16,\$0' +.*:57: Warning: extended operand requested but not required +.*:59: Warning: extended operand requested but not required +.*:60: Warning: extended operand requested but not required +.*:62: Error: opcode not supported on this processor: mips32 \(mips32\) `sd\.e \$16,0\(\$16\)' +.*:64: Warning: extended operand requested but not required +.*:66: Warning: extended operand requested but not required +.*:68: Warning: extended operand requested but not required +.*:70: Warning: extended operand requested but not required +.*:72: Warning: extended operand requested but not required +.*:74: Warning: extended operand requested but not required +.*:77: Warning: extended operand requested but not required +.*:80: Error: opcode not supported on this processor: mips32 \(mips32\) `lwu\.e \$16,0\(\$16\)' +.*:82: Warning: extended operand requested but not required +.*:84: Warning: extended operand requested but not required +.*:86: Warning: extended operand requested but not required +.*:88: Warning: extended operand requested but not required +.*:90: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,\$16,\$16' +.*:91: Error: invalid operands `addu\.e \$16,\$16,\$16' +.*:92: Error: opcode not supported on this processor: mips32 \(mips32\) `dsubu\.e \$16,\$16,\$16' +.*:93: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$16,\$16,\$16' +.*:95: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$16' +.*:97: Error: unrecognized extended version of MIPS16 opcode `j\.e \$16' +.*:99: Error: unrecognized extended version of MIPS16 opcode `jr\.e \$31' +.*:101: Error: unrecognized extended version of MIPS16 opcode `j\.e \$31' +.*:103: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$16' +.*:105: Error: unrecognized extended version of MIPS16 opcode `jalr\.e \$31,\$16' +.*:107: Error: operand 1 must be an immediate expression `jal\.e \$16' +.*:109: Error: operand 1 must be an immediate expression `jal\.e \$31,\$16' +.*:111: Error: unrecognized extended version of MIPS16 opcode `jrc\.e \$16' +.*:112: Error: unrecognized extended version of MIPS16 opcode `jrc\.e \$31' +.*:113: Error: unrecognized extended version of MIPS16 opcode `jalrc\.e \$16' +.*:114: Error: unrecognized extended version of MIPS16 opcode `jalrc\.e \$31,\$16' +.*:115: Error: unrecognized extended version of MIPS16 opcode `sdbbp\.e 0' +.*:116: Error: invalid operands `slt\.e \$16,\$16' +.*:117: Error: invalid operands `sltu\.e \$16,\$16' +.*:118: Error: unrecognized extended version of MIPS16 opcode `sllv\.e \$16,\$16' +.*:119: Error: invalid operands `sll\.e \$16,\$16' +.*:120: Error: unrecognized extended version of MIPS16 opcode `break\.e 0' +.*:121: Error: unrecognized extended version of MIPS16 opcode `srlv\.e \$16,\$16' +.*:122: Error: invalid operands `srl\.e \$16,\$16' +.*:123: Error: unrecognized extended version of MIPS16 opcode `srav\.e \$16,\$16' +.*:124: Error: invalid operands `sra\.e \$16,\$16' +.*:125: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrl\.e \$16,8' +.*:126: Error: unrecognized extended version of MIPS16 opcode `entry\.e ' +.*:127: Error: unrecognized extended version of MIPS16 opcode `entry\.e \$31' +.*:128: Error: unrecognized extended version of MIPS16 opcode `exit\.e \$f0' +.*:129: Error: unrecognized extended version of MIPS16 opcode `exit\.e' +.*:130: Error: invalid operands `cmp\.e \$16,\$16' +.*:131: Error: unrecognized extended version of MIPS16 opcode `neg\.e \$16,\$16' +.*:132: Error: unrecognized extended version of MIPS16 opcode `and\.e \$16,\$16' +.*:133: Error: unrecognized extended version of MIPS16 opcode `or\.e \$16,\$16' +.*:134: Error: unrecognized extended version of MIPS16 opcode `xor\.e \$16,\$16' +.*:135: Error: unrecognized extended version of MIPS16 opcode `not\.e \$16,\$16' +.*:136: Error: unrecognized extended version of MIPS16 opcode `mfhi\.e \$16' +.*:137: Error: unrecognized extended version of MIPS16 opcode `zeb\.e \$16' +.*:138: Error: unrecognized extended version of MIPS16 opcode `zeh\.e \$16' +.*:139: Error: opcode not supported on this processor: mips32 \(mips32\) `zew\.e \$16' +.*:140: Error: unrecognized extended version of MIPS16 opcode `seb\.e \$16' +.*:141: Error: unrecognized extended version of MIPS16 opcode `seh\.e \$16' +.*:142: Error: opcode not supported on this processor: mips32 \(mips32\) `sew\.e \$16' +.*:143: Error: unrecognized extended version of MIPS16 opcode `mflo\.e \$16' +.*:144: Error: opcode not supported on this processor: mips32 \(mips32\) `dsra\.e \$16,8' +.*:145: Error: opcode not supported on this processor: mips32 \(mips32\) `dsllv\.e \$16,\$16' +.*:146: Error: opcode not supported on this processor: mips32 \(mips32\) `dsll\.e \$16,\$16' +.*:147: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrlv\.e \$16,\$16' +.*:148: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrl\.e \$16,\$16' +.*:149: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrav\.e \$16,\$16' +.*:150: Error: opcode not supported on this processor: mips32 \(mips32\) `dsra\.e \$16,\$16' +.*:151: Error: unrecognized extended version of MIPS16 opcode `mult\.e \$16,\$16' +.*:152: Error: unrecognized extended version of MIPS16 opcode `multu\.e \$16,\$16' +.*:153: Error: unrecognized extended version of MIPS16 opcode `div\.e \$0,\$16,\$16' +.*:154: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$0,\$16,\$16' +.*:155: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$0,\$16,\$16' +.*:156: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$0,\$16,\$16' +.*:157: Error: opcode not supported on this processor: mips32 \(mips32\) `dmult\.e \$16,\$16' +.*:158: Error: opcode not supported on this processor: mips32 \(mips32\) `dmultu\.e \$16,\$16' +.*:159: Error: opcode not supported on this processor: mips32 \(mips32\) `ddiv\.e \$0,\$16,\$16' +.*:160: Error: opcode not supported on this processor: mips32 \(mips32\) `drem\.e \$0,\$16,\$16' +.*:161: Error: opcode not supported on this processor: mips32 \(mips32\) `ddivu\.e \$0,\$16,\$16' +.*:162: Error: opcode not supported on this processor: mips32 \(mips32\) `dremu\.e \$0,\$16,\$16' +.*:164: Error: unrecognized extended version of MIPS16 opcode `extend\.e 0' +.*:166: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.e \$16,0\(\$29\)' +.*:167: Error: opcode not supported on this processor: mips32 \(mips32\) `sd\.e \$16,0\(\$29\)' +.*:168: Error: opcode not supported on this processor: mips32 \(mips32\) `sd\.e \$31,0\(\$29\)' +.*:169: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$29,0' +.*:170: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$29,\$29,0' +.*:171: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$29,0' +.*:172: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$29,\$29,0' +.*:174: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.e \$16,0\(\$pc\)' +.*:175: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.e \$16,\.-3' +.*:176: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$16,0' +.*:177: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,0' +.*:179: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$16,\$pc,0' +.*:180: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,\$pc,0' +.*:181: Error: opcode not supported on this processor: mips32 \(mips32\) `dla\.e \$16,\.-1' +.*:182: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.e \$16,\$sp,0' +.*:183: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.e \$16,\$sp,0' +.*:10: Warning: extended operand requested but not required +.*:12: Warning: extended operand requested but not required +.*:19: Warning: extended operand requested but not required +.*:21: Warning: extended operand requested but not required +.*:44: Warning: extended operand requested but not required +.*:45: Warning: extended operand requested but not required diff --git a/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.d b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.d new file mode 100644 index 0000000..3c677cf --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.d @@ -0,0 +1,4 @@ +#as: -32 +#name: MIPS16 explicit unextended instructions +#error-output: mips16e-32@mips16-insn-t.l +#source: mips16-insn-t.s diff --git a/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.l b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.l new file mode 100644 index 0000000..69ce411 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e-32@mips16-insn-t.l @@ -0,0 +1,43 @@ +.*: Assembler messages: +.*:14: Error: invalid operands `jal\.t 0' +.*:16: Error: unrecognized unextended version of MIPS16 opcode `jalx\.t 0' +.*:24: Error: opcode not supported on this processor: mips32 \(mips32\) `dsll\.t \$16,\$16,8' +.*:28: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.t \$16,0\(\$16\)' +.*:32: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$16,\$16,0' +.*:33: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,\$16,0' +.*:62: Error: opcode not supported on this processor: mips32 \(mips32\) `sd\.t \$16,0\(\$16\)' +.*:80: Error: opcode not supported on this processor: mips32 \(mips32\) `lwu\.t \$16,0\(\$16\)' +.*:90: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,\$16,\$16' +.*:92: Error: opcode not supported on this processor: mips32 \(mips32\) `dsubu\.t \$16,\$16,\$16' +.*:125: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrl\.t \$16,8' +.*:139: Error: opcode not supported on this processor: mips32 \(mips32\) `zew\.t \$16' +.*:142: Error: opcode not supported on this processor: mips32 \(mips32\) `sew\.t \$16' +.*:144: Error: opcode not supported on this processor: mips32 \(mips32\) `dsra\.t \$16,8' +.*:145: Error: opcode not supported on this processor: mips32 \(mips32\) `dsllv\.t \$16,\$16' +.*:146: Error: opcode not supported on this processor: mips32 \(mips32\) `dsll\.t \$16,\$16' +.*:147: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrlv\.t \$16,\$16' +.*:148: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrl\.t \$16,\$16' +.*:149: Error: opcode not supported on this processor: mips32 \(mips32\) `dsrav\.t \$16,\$16' +.*:150: Error: opcode not supported on this processor: mips32 \(mips32\) `dsra\.t \$16,\$16' +.*:157: Error: opcode not supported on this processor: mips32 \(mips32\) `dmult\.t \$16,\$16' +.*:158: Error: opcode not supported on this processor: mips32 \(mips32\) `dmultu\.t \$16,\$16' +.*:159: Error: opcode not supported on this processor: mips32 \(mips32\) `ddiv\.t \$0,\$16,\$16' +.*:160: Error: opcode not supported on this processor: mips32 \(mips32\) `drem\.t \$0,\$16,\$16' +.*:161: Error: opcode not supported on this processor: mips32 \(mips32\) `ddivu\.t \$0,\$16,\$16' +.*:162: Error: opcode not supported on this processor: mips32 \(mips32\) `dremu\.t \$0,\$16,\$16' +.*:166: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.t \$16,0\(\$29\)' +.*:167: Error: opcode not supported on this processor: mips32 \(mips32\) `sd\.t \$16,0\(\$29\)' +.*:168: Error: opcode not supported on this processor: mips32 \(mips32\) `sd\.t \$31,0\(\$29\)' +.*:169: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$29,0' +.*:170: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$29,\$29,0' +.*:171: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$29,0' +.*:172: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$29,\$29,0' +.*:174: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.t \$16,0\(\$pc\)' +.*:175: Error: opcode not supported on this processor: mips32 \(mips32\) `ld\.t \$16,\.-3' +.*:176: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$16,0' +.*:177: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,0' +.*:179: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$16,\$pc,0' +.*:180: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,\$pc,0' +.*:181: Error: opcode not supported on this processor: mips32 \(mips32\) `dla\.t \$16,\.-1' +.*:182: Error: opcode not supported on this processor: mips32 \(mips32\) `daddiu\.t \$16,\$sp,0' +.*:183: Error: opcode not supported on this processor: mips32 \(mips32\) `daddu\.t \$16,\$sp,0' diff --git a/gas/testsuite/gas/mips/mips16e-32@mips16-macro-e.l b/gas/testsuite/gas/mips/mips16e-32@mips16-macro-e.l index eb763b5..b91a274 100644 --- a/gas/testsuite/gas/mips/mips16e-32@mips16-macro-e.l +++ b/gas/testsuite/gas/mips/mips16e-32@mips16-macro-e.l @@ -1,20 +1,20 @@ .*: Assembler messages: -.*:4: Error: invalid operands `div\.e \$2,\$3,\$4' -.*:5: Error: invalid operands `divu\.e \$3,\$4,\$5' +.*:4: Error: unrecognized extended version of MIPS16 opcode `div\.e \$2,\$3,\$4' +.*:5: Error: unrecognized extended version of MIPS16 opcode `divu\.e \$3,\$4,\$5' .*:6: Error: opcode not supported on this processor: mips32 \(mips32\) `ddiv\.e \$4,\$5,\$6' .*:7: Error: opcode not supported on this processor: mips32 \(mips32\) `ddivu\.e \$5,\$6,\$7' -.*:8: Error: invalid operands `rem\.e \$6,\$7,\$16' -.*:9: Error: invalid operands `remu\.e \$6,\$7,\$17' +.*:8: Error: unrecognized extended version of MIPS16 opcode `rem\.e \$6,\$7,\$16' +.*:9: Error: unrecognized extended version of MIPS16 opcode `remu\.e \$6,\$7,\$17' .*:10: Error: opcode not supported on this processor: mips32 \(mips32\) `drem\.e \$2,\$3,\$4' .*:11: Error: opcode not supported on this processor: mips32 \(mips32\) `dremu\.e \$3,\$4,\$5' .*:12: Error: unrecognized extended version of MIPS16 opcode `mul\.e \$4,\$5,\$6' .*:13: Error: opcode not supported on this processor: mips32 \(mips32\) `dmul\.e \$5,\$6,\$7' -.*:14: Error: invalid operands `subu\.e \$2,-32767' -.*:15: Error: invalid operands `subu\.e \$3,16' -.*:16: Error: invalid operands `subu\.e \$4,32768' -.*:17: Error: invalid operands `subu\.e \$3,\$7,-16383' -.*:18: Error: invalid operands `subu\.e \$4,\$16,4' -.*:19: Error: invalid operands `subu\.e \$5,\$17,16384' +.*:14: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$2,-32767' +.*:15: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,16' +.*:16: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,32768' +.*:17: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$3,\$7,-16383' +.*:18: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$4,\$16,4' +.*:19: Error: unrecognized extended version of MIPS16 opcode `subu\.e \$5,\$17,16384' .*:20: Error: opcode not supported on this processor: mips32 \(mips32\) `dsubu\.e \$4,-32767' .*:21: Error: opcode not supported on this processor: mips32 \(mips32\) `dsubu\.e \$6,6' .*:22: Error: opcode not supported on this processor: mips32 \(mips32\) `dsubu\.e \$7,32768' diff --git a/include/ChangeLog b/include/ChangeLog index 2f76430..f771bd1 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + + * opcode/mips.h (INSN2_SHORT_ONLY): New macro. + 2016-12-21 Alan Modra <amodra@gmail.com> * coff/pe.h: Fix comment chars with high bit set. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 329a698..cf661c8 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1114,6 +1114,10 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 /* Instruction has a forbidden slot. */ #define INSN2_FORBIDDEN_SLOT 0x00008000 +/* Opcode table entry is for a short MIPS16 form only. An extended + encoding may still exist, but with a separate opcode table entry + required. */ +#define INSN2_SHORT_ONLY 0x00010000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index cb69f64..46b9d83 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,20 @@ 2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix + matching for INSN2_SHORT_ONLY opcode table entries. + * mips16-opc.c (SH): New macro. + (mips16_opcodes): Set SH in `pinfo2' for non-extensible + instruction entries: "nop", "addu", "and", "break", "cmp", + "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", + "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", + "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", + "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", + "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", + "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", + "seh", "sew", "zeb", "zeh", "zew" and "extend". + +2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended encoding support. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 4bc1f59..ade5136 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -2129,6 +2129,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) } else if ((first & 0xf800) == 0xf000 && have_second + && !(op->pinfo2 & INSN2_SHORT_ONLY) && (second & op->mask) == op->match) match = MATCH_FULL; else diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index a6f6ad1..0c1c7fa 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -170,6 +170,8 @@ decode_mips16_operand (char type, bfd_boolean extended_p) #define UBR INSN2_UNCOND_BRANCH #define CBR INSN2_COND_BRANCH +#define SH INSN2_SHORT_ONLY + #define I1 INSN_ISA1 #define I3 INSN_ISA3 #define I32 INSN_ISA32 @@ -179,7 +181,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p) const struct mips_opcode mips16_opcodes[] = { /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ -{"nop", "", 0x6500, 0xffff, 0, RD_16, I1, 0, 0 }, /* move $0,$Z */ +{"nop", "", 0x6500, 0xffff, 0, SH|RD_16, I1, 0, 0 }, /* move $0,$Z */ {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, {"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, {"addiu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, @@ -188,14 +190,14 @@ const struct mips_opcode mips16_opcodes[] = {"addiu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, -{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }, {"addu", "y,x,4", 0x4000, 0xf810, WR_1|RD_2, 0, I1, 0, 0 }, {"addu", "x,k", 0x4800, 0xf800, MOD_1, 0, I1, 0, 0 }, {"addu", "S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, {"addu", "S,S,K", 0x6300, 0xff00, 0, MOD_SP, I1, 0, 0 }, {"addu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, I1, 0, 0 }, {"addu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, -{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, +{"and", "x,y", 0xe80c, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, {"b", "q", 0x1000, 0xf800, 0, UBR, I1, 0, 0 }, {"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 }, {"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, @@ -219,11 +221,11 @@ const struct mips_opcode mips16_opcodes[] = {"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 }, {"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, {"bnez", "x,p", 0x2800, 0xf800, RD_1, CBR, I1, 0, 0 }, -{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1, 0, 0 }, +{"break", "6", 0xe805, 0xf81f, TRAP, SH, I1, 0, 0 }, {"bteqz", "p", 0x6000, 0xff00, RD_T, CBR, I1, 0, 0 }, {"btnez", "p", 0x6100, 0xff00, RD_T, CBR, I1, 0, 0 }, {"cmpi", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 }, +{"cmp", "x,y", 0xe80a, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, {"cmp", "x,U", 0x7000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, {"dla", "y,E", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"daddiu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, @@ -232,63 +234,63 @@ const struct mips_opcode mips16_opcodes[] = {"daddiu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, {"daddiu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"daddiu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, -{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 }, {"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 }, {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 }, {"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, {"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 }, {"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 }, {"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 }, -{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, +{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 }, -{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, +{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 }, -{"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, +{"div", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, -{"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, +{"divu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, {"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 }, -{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I3, 0, 0 }, -{"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, +{"dmult", "x,y", 0xe81c, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, +{"dmultu", "x,y", 0xe81d, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I3, 0, 0 }, +{"drem", "0,x,y", 0xe81e, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 }, -{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I3, 0, 0 }, +{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I3, 0, 0 }, {"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 }, -{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, +{"dsllv", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, {"dsll", "x,w,[", 0x3001, 0xf803, WR_1|RD_2, 0, I3, 0, 0 }, -{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, -{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, +{"dsll", "y,x", 0xe814, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{"dsrav", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, {"dsra", "y,]", 0xe813, 0xf81f, MOD_1, 0, I3, 0, 0 }, -{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, -{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, +{"dsra", "y,x", 0xe817, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{"dsrlv", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, {"dsrl", "y,]", 0xe808, 0xf81f, MOD_1, 0, I3, 0, 0 }, -{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, 0, I3, 0, 0 }, -{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, +{"dsrl", "y,x", 0xe816, 0xf81f, MOD_1|RD_2, SH, I3, 0, 0 }, +{"dsubu", "z,v,y", 0xe002, 0xf803, WR_1|RD_2|RD_3, SH, I3, 0, 0 }, {"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 }, {"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I3, 0, 0 }, -{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 }, -{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1, 0, 0 }, -{"exit", "", 0xef09, 0xffff, TRAP, 0, I1, 0, 0 }, -{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1, 0, 0 }, -{"entry", "", 0xe809, 0xffff, TRAP, 0, I1, 0, 0 }, -{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1, 0, 0 }, -{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, 0, I1, 0, 0 }, -{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, 0, I1, 0, 0 }, -{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, 0, I1, 0, 0 }, -{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, 0, I1, 0, 0 }, +{"exit", "L", 0xed09, 0xff1f, TRAP, SH, I1, 0, 0 }, +{"exit", "L", 0xee09, 0xff1f, TRAP, SH, I1, 0, 0 }, +{"exit", "", 0xef09, 0xffff, TRAP, SH, I1, 0, 0 }, +{"exit", "L", 0xef09, 0xff1f, TRAP, SH, I1, 0, 0 }, +{"entry", "", 0xe809, 0xffff, TRAP, SH, I1, 0, 0 }, +{"entry", "l", 0xe809, 0xf81f, TRAP, SH, I1, 0, 0 }, +{"jalr", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 }, +{"jalr", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 }, +{"jal", "x", 0xe840, 0xf8ff, RD_1|WR_31|UBD, SH, I1, 0, 0 }, +{"jal", "R,x", 0xe840, 0xf8ff, RD_2|WR_31|UBD, SH, I1, 0, 0 }, {"jal", "a", 0x18000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, {"jalx", "i", 0x1c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, -{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, 0, I1, 0, 0 }, -{"jr", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 }, -{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, 0, I1, 0, 0 }, -{"j", "R", 0xe820, 0xffff, UBD, RD_31, I1, 0, 0 }, +{"jr", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }, +{"jr", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 }, +{"j", "x", 0xe800, 0xf8ff, RD_1|UBD, SH, I1, 0, 0 }, +{"j", "R", 0xe820, 0xffff, UBD, SH|RD_31, I1, 0, 0 }, /* MIPS16e compact jumps. We keep them near the ordinary jumps so that we easily find them when converting a normal jump to a compact one. */ -{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, UBR, I32, 0, 0 }, -{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, UBR, I32, 0, 0 }, -{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, UBR, I32, 0, 0 }, -{"jrc", "R", 0xe8a0, 0xffff, NODS, RD_31|UBR, I32, 0, 0 }, +{"jalrc", "x", 0xe8c0, 0xf8ff, RD_1|WR_31|NODS, SH|UBR, I32, 0, 0 }, +{"jalrc", "R,x", 0xe8c0, 0xf8ff, RD_2|WR_31|NODS, SH|UBR, I32, 0, 0 }, +{"jrc", "x", 0xe880, 0xf8ff, RD_1|NODS, SH|UBR, I32, 0, 0 }, +{"jrc", "R", 0xe8a0, 0xffff, NODS, SH|RD_31|UBR, I32, 0, 0 }, {"lb", "y,5(x)", 0x8000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, {"lbu", "y,5(x)", 0xa000, 0xf800, WR_1|RD_3, 0, I1, 0, 0 }, {"ld", "y,D(x)", 0x3800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, @@ -303,60 +305,60 @@ const struct mips_opcode mips16_opcodes[] = {"lw", "x,V(P)", 0xb000, 0xf800, WR_1, RD_PC, I1, 0, 0 }, {"lw", "x,V(S)", 0x9000, 0xf800, WR_1, RD_SP, I1, 0, 0 }, {"lwu", "y,W(x)", 0xb800, 0xf800, WR_1|RD_3, 0, I3, 0, 0 }, -{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, 0, I1, 0, 0 }, -{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, 0, I1, 0, 0 }, -{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, 0, I1, 0, 0 }, -{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, 0, I1, 0, 0 }, +{"mfhi", "x", 0xe810, 0xf8ff, WR_1|RD_HI, SH, I1, 0, 0 }, +{"mflo", "x", 0xe812, 0xf8ff, WR_1|RD_LO, SH, I1, 0, 0 }, +{"move", "y,X", 0x6700, 0xff00, WR_1|RD_2, SH, I1, 0, 0 }, +{"move", "Y,Z", 0x6500, 0xff00, WR_1|RD_2, SH, I1, 0, 0 }, {"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 }, -{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I1, 0, 0 }, -{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, 0, I1, 0, 0 }, -{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, 0, I1, 0, 0 }, -{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, 0, I1, 0, 0 }, -{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, -{"rem", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, +{"mult", "x,y", 0xe818, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 }, +{"multu", "x,y", 0xe819, 0xf81f, RD_1|RD_2|WR_HI|WR_LO, SH, I1, 0, 0 }, +{"neg", "x,w", 0xe80b, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, +{"not", "x,w", 0xe80f, 0xf81f, WR_1|RD_2, SH, I1, 0, 0 }, +{"or", "x,y", 0xe80d, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{"rem", "0,x,y", 0xe81a, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, -{"remu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, 0, I1, 0, 0 }, +{"remu", "0,x,y", 0xe81b, 0xf81f, RD_2|RD_3|WR_HI|WR_LO, SH, I1, 0, 0 }, {"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, {"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, {"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 }, {"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 }, {"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I3, 0, 0 }, {"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, -{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, +{"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, {"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, -{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, +{"sll", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, {"slti", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 }, +{"slt", "x,y", 0xe802, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, {"slt", "x,8", 0x5000, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, {"sltiu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, 0, I1, 0, 0 }, +{"sltu", "x,y", 0xe803, 0xf81f, RD_1|RD_2|WR_T, SH, I1, 0, 0 }, {"sltu", "x,8", 0x5800, 0xf800, RD_1|WR_T, 0, I1, 0, 0 }, -{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, +{"srav", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, {"sra", "x,w,<", 0x3003, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, -{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, -{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, +{"sra", "y,x", 0xe807, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{"srlv", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, {"srl", "x,w,<", 0x3002, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, -{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, -{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{"srl", "y,x", 0xe806, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, +{"subu", "z,v,y", 0xe003, 0xf803, WR_1|RD_2|RD_3, SH, I1, 0, 0 }, {"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 }, {"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 }, {"sw", "y,W(x)", 0xd800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, {"sw", "x,V(S)", 0xd000, 0xf800, RD_1, RD_SP, I1, 0, 0 }, {"sw", "R,V(S)", 0x6200, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 }, -{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, +{"xor", "x,y", 0xe80e, 0xf81f, MOD_1|RD_2, SH, I1, 0, 0 }, /* MIPS16e additions; see above for compact jumps. */ {"restore", "M", 0x6400, 0xff80, WR_31|NODS, MOD_SP, I32, 0, 0 }, {"save", "m", 0x6480, 0xff80, NODS, RD_31|MOD_SP, I32, 0, 0 }, -{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32, 0, 0 }, -{"seb", "x", 0xe891, 0xf8ff, MOD_1, 0, I32, 0, 0 }, -{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, 0, I32, 0, 0 }, -{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, 0, I64, 0, 0 }, -{"zeb", "x", 0xe811, 0xf8ff, MOD_1, 0, I32, 0, 0 }, -{"zeh", "x", 0xe831, 0xf8ff, MOD_1, 0, I32, 0, 0 }, -{"zew", "x", 0xe851, 0xf8ff, MOD_1, 0, I64, 0, 0 }, +{"sdbbp", "6", 0xe801, 0xf81f, TRAP, SH, I32, 0, 0 }, +{"seb", "x", 0xe891, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{"seh", "x", 0xe8b1, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{"sew", "x", 0xe8d1, 0xf8ff, MOD_1, SH, I64, 0, 0 }, +{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 }, +{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 }, /* Place EXTEND last so that it catches any prefix that didn't match anything. */ -{"extend", "e", 0xf000, 0xf800, NODS, 0, I1, 0, 0 }, +{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 }, }; const int bfd_mips16_num_opcodes = |