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| author | Jiong Wang <jiwang@sourceware.org> | 2013-03-01 06:42:18 +0000 |
|---|---|---|
| committer | Jiong Wang <jiwang@sourceware.org> | 2013-03-01 06:42:18 +0000 |
| commit | c32f23033e497f3f10f8e8e0943341978bbb9a9a (patch) | |
| tree | dbf34ca3d721c9315613ab9bf1adef2df3a1575e | |
| parent | cd143fbbeac7ce8def14a73c088cf586cb85c8a9 (diff) | |
| download | gdb-c32f23033e497f3f10f8e8e0943341978bbb9a9a.zip gdb-c32f23033e497f3f10f8e8e0943341978bbb9a9a.tar.gz gdb-c32f23033e497f3f10f8e8e0943341978bbb9a9a.tar.bz2 | |
Add missing file from the previous commit.
(forget to "cvs add" it)
| -rw-r--r-- | gdb/regformats/reg-tilegx32.dat | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/gdb/regformats/reg-tilegx32.dat b/gdb/regformats/reg-tilegx32.dat new file mode 100644 index 0000000..d8bfe2a --- /dev/null +++ b/gdb/regformats/reg-tilegx32.dat @@ -0,0 +1,67 @@ +name:tilegx32 +expedite:sp,lr,pc +64:r0 +64:r1 +64:r2 +64:r3 +64:r4 +64:r5 +64:r6 +64:r7 +64:r8 +64:r9 +64:r10 +64:r11 +64:r12 +64:r13 +64:r14 +64:r15 +64:r16 +64:r17 +64:r18 +64:r19 +64:r20 +64:r21 +64:r22 +64:r23 +64:r24 +64:r25 +64:r26 +64:r27 +64:r28 +64:r29 +64:r30 +64:r31 +64:r32 +64:r33 +64:r34 +64:r35 +64:r36 +64:r37 +64:r38 +64:r39 +64:r40 +64:r41 +64:r42 +64:r43 +64:r44 +64:r45 +64:r46 +64:r47 +64:r48 +64:r49 +64:r50 +64:r51 +64:r52 +64:tp +64:sp +64:lr +64:sn +64:io0 +64:io1 +64:us0 +64:us1 +64:us2 +64:us3 +64:zero +32:pc |