aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAdam Nemet <anemet@caviumnetworks.com>2008-02-04 19:20:16 +0000
committerAdam Nemet <anemet@caviumnetworks.com>2008-02-04 19:20:16 +0000
commit967344c664dc29bd186de2502441af112655c822 (patch)
tree6ebecd27cb0de1e4683628bd6aa797d0c738bceb
parent61d4e56d1ba59b80d30efceb4b303bb27aa4510a (diff)
downloadgdb-967344c664dc29bd186de2502441af112655c822.zip
gdb-967344c664dc29bd186de2502441af112655c822.tar.gz
gdb-967344c664dc29bd186de2502441af112655c822.tar.bz2
* config/tc-mips.c (mips_cpu_info_table): Add Octeon.
-rw-r--r--gas/ChangeLog4
-rw-r--r--gas/config/tc-mips.c3
2 files changed, 7 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2ecfdef..29813e9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add Octeon.
+
2008-01-31 Marc Gauthier <marc@tensilica.com>
* configure.tgt (xtensa*-*-*): Recognize processor variants.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index e29041c..f089345 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -14865,6 +14865,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
{ "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
+ /* Cavium Networks Octeon CPU core */
+ { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
+
/* End marker */
{ NULL, 0, 0, 0 }
};