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authorAndreas Krebbel <krebbel@linux.vnet.ibm.com>2017-05-29 12:38:11 +0200
committerAndreas Krebbel <krebbel@linux.vnet.ibm.com>2017-05-30 10:35:55 +0200
commit67aa8be4cb43cd94bc322fed8bdba48b3c8719c4 (patch)
treef96534567dc84ff15b4a18f70a021fae989c8a87
parentffc61c5de1a5a89e3e37fb9376725c32a839c34d (diff)
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S/390: Add missing operand to tb instruction
gas/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/s390/esa-g5.d: Add missing operand to tb instruction. * testsuite/gas/s390/esa-g5.s: Likewise. opcodes/ChangeLog: 2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.txt: Add missing operand to tb instruction.
-rw-r--r--gas/testsuite/gas/s390/esa-g5.d2
-rw-r--r--gas/testsuite/gas/s390/esa-g5.s2
-rw-r--r--opcodes/s390-opc.txt2
3 files changed, 3 insertions, 3 deletions
diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
index 07da026..5d53caf 100644
--- a/gas/testsuite/gas/s390/esa-g5.d
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -443,7 +443,7 @@ Disassembly of section .text:
.*: b3 4b 00 58 [ ]*sxbr %f5,%f8
.*: 37 58 [ ]*sxr %f5,%f8
.*: b2 4c 00 69 [ ]*tar %a6,%r9
-.*: b2 2c 00 06 [ ]*tb %r6
+.*: b2 2c 00 69 [ ]*tb %r6,%r9
.*: b3 51 50 69 [ ]*tbdr %f6,5,%f9
.*: b3 50 50 69 [ ]*tbedr %f6,5,%f9
.*: ed 65 af ff 00 11 [ ]*tcdb %f6,4095\(%r5,%r10\)
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
index 6b2a029..75d97fd 100644
--- a/gas/testsuite/gas/s390/esa-g5.s
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -437,7 +437,7 @@ foo:
sxbr %f5,%f8
sxr %f5,%f8
tar %a6,%r9
- tb %r6
+ tb %r6,%r9
tbdr %r6,5,%r9
tbedr %r6,5,%r9
tcdb %f6,4095(%r5,%r10)
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index f759486..eed7332 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -228,7 +228,7 @@ b246 stura RRE_RR "store using real address" g5 esa,zarch
2f swr RR_FF "subtract unnormalized (long)" g5 esa,zarch
37 sxr RR_FEFE "subtract normalized (ext.)" g5 esa,zarch
b24c tar RRE_AR "test access" g5 esa,zarch
-b22c tb RRE_0R "test block" g5 esa,zarch
+b22c tb RRE_RR "test block" g5 esa,zarch
91 tm SI_URD "test under mask" g5 esa,zarch
b236 tpi S_RD "test pending interruption" g5 esa,zarch
e501 tprot SSE_RDRD "test protection" g5 esa,zarch