[MIPS] Map 'move' to 'or'.

The MIPS assembly idiom 'move' now maps to the 'or' machine instruction. This change affects microMIPS, MIPS32, MIPS64. 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> opcodes/ * micromips-opc.c (micromips_opcodes): Re-order table so that move based on 'or' is first. * mips-opc.c (mips_builtin_opcodes): Ditto. bfd/ * elfxx-mips.c (STUB_MOVE): Change to use 'or' only. (mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry, mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry): Update to use 'or' instead of 'addu/daddu'. (_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE. (move_insns_32): Reorder table. gas/ * config/tc-mips.c (move_register): Change to use 'or' only. (s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to use or for move. gas/testsuite/ * gas/mips/elf-rel23.d: Update test. * gas/mips/elf-rel23.d: Ditto. * gas/mips/elf-rel23a.d: Ditto. * gas/mips/elf-rel23b.d: Ditto. * gas/mips/elf_e_flags1.d: Ditto. * gas/mips/elf_e_flags2.d: Ditto. * gas/mips/elf_e_flags3.d: Ditto. * gas/mips/elf_e_flags4.d: Ditto. * gas/mips/loc-swap-dis.d: Ditto. * gas/mips/micromips-insn32.d: Ditto. * gas/mips/micromips-noinsn32.d: Ditto. * gas/mips/micromips-trap.d: Ditto. * gas/mips/micromips.d: Ditto. * gas/mips/mips-abi32-pic.d: Ditto. * gas/mips/mips-abi32.d: Ditto. * gas/mips/mips-gp32-fp32-pic.d: Ditto. * gas/mips/mips-gp32-fp32.d: Ditto. * gas/mips/mips-gp32-fp64-pic.d: Ditto. * gas/mips/mips-gp32-fp64.d: Ditto. * gas/mips/mips-gp64-fp32-pic.d: Ditto. * gas/mips/mips-gp64-fp32.d: Ditto. * gas/mips/mips-gp64-fp64-pic.d: Ditto. * gas/mips/mips-gp64-fp64.d: Ditto. * gas/mips/mipsr6@loc-swap-dis.d: Ditto. * gas/mips/tls-o32.d: Ditto. * gas/mips/uld2-eb.d: Ditto. * gas/mips/uld2-el.d: Ditto. * gas/mips/ulw2-eb-ilocks.d: Ditto. * gas/mips/ulw2-eb.d: Ditto. * gas/mips/ulw2-el-ilocks.d: Ditto. * gas/mips/ulw2-el.d: Ditto. * gas/mips/move.d: New test. * gas/mips/move.s: Ditto. * gas/mips/micromips32-move.d: Ditto. * gas/mips/micromips32-move.s: Ditto. * gas/mips/mips.exp: Run the new tests. gold/ * mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64, lazy_stub_normal_1, lazy_stub_normal_1_n64, lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big, lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64, lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big, lazy_stub_micromips32_big_n64): Update to use 'or' for move instead of 'addu/daddu'. ld/testsuite/ * ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test. * ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-se.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto. * ld-mips-elf/jalx-2.dd: Ditto. * ld-mips-elf/mips16-pic-3.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3a.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-5b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto. * ld-mips-elf/stub-dynsym-1-10000.d: Ditto. * ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto. * ld-mips-elf/stub-dynsym-1-7fff.d: Ditto. * ld-mips-elf/stub-dynsym-1-8000.d: Ditto. * ld-mips-elf/stub-dynsym-1-fff0.d: Ditto. * ld-mips-elf/tlsbin-o32.d: Ditto. * ld-mips-elf/tlsdyn-o32-1.d: Ditto. * ld-mips-elf/tlsdyn-o32-2.d: Ditto. * ld-mips-elf/tlsdyn-o32-3.d: Ditto. * ld-mips-elf/tlsdyn-o32.d: Ditto. * ld-mips-elf/tlslib-o32.d: Ditto.
author: Simon Dardis <simon.dardis@imgtec.com> 2015-08-12 17:06:35 +0100
committer: Robert Suchanek <robert.suchanek@imgtec.com> 2015-08-12 17:10:22 +0100
commit: 40fc1451c63d21a1448bb21e39a7b70ecb959213 (patch)
tree: a614e0a966ad575b5315d7dd97f633dd1adf30e3
parent: b6dafabfb18e3ab207a1818ebe68e30337b5515d (diff)
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gdb-40fc1451c63d21a1448bb21e39a7b70ecb959213.tar.gz
gdb-40fc1451c63d21a1448bb21e39a7b70ecb959213.tar.bz2
75 files changed, 393 insertions, 285 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 2f850e7..e561764 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,12 @@
+2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* elfxx-mips.c (STUB_MOVE): Change to use 'or' only.
+	(mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry,
+	mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry):
+	Update to use 'or' instead of 'addu/daddu'.
+	(_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE.
+	(move_insns_32): Reorder table.
+
 2015-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* elf32-i386.c (elf_i386_relocate_section): Properly skip IFUNC
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 06e8158..eb7593a 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -911,10 +911,7 @@ static bfd *reldyn_sorting_bfd;
   ((ABI_64_P (abfd)							\
     ? 0xdf998010				/* ld t9,0x8010(gp) */	\
     : 0x8f998010))              		/* lw t9,0x8010(gp) */
-#define STUB_MOVE(abfd)							\
-   ((ABI_64_P (abfd)							\
-     ? 0x03e0782d				/* daddu t7,ra */	\
-     : 0x03e07821))				/* addu t7,ra */
+#define STUB_MOVE 0x03e07825			/* or t7,ra,zero */
 #define STUB_LUI(VAL) (0x3c180000 + (VAL))	/* lui t8,VAL */
 #define STUB_JALR 0x0320f809			/* jalr t9,ra */
 #define STUB_ORI(VAL) (0x37180000 + (VAL))	/* ori t8,t8,VAL */
@@ -930,10 +927,7 @@ static bfd *reldyn_sorting_bfd;
    ? 0xdf3c8010					/* ld t9,0x8010(gp) */	\
    : 0xff3c8010)				/* lw t9,0x8010(gp) */
 #define STUB_MOVE_MICROMIPS 0x0dff		/* move t7,ra */
-#define STUB_MOVE32_MICROMIPS(abfd)					\
-   (ABI_64_P (abfd)							\
-    ? 0x581f7950				/* daddu t7,ra,zero */	\
-    : 0x001f7950)				/* addu t7,ra,zero */
+#define STUB_MOVE32_MICROMIPS 0x001f7a90	/* or t7,ra,zero */
 #define STUB_LUI_MICROMIPS(VAL)						\
    (0x41b80000 + (VAL))				/* lui t8,VAL */
 #define STUB_JALR_MICROMIPS 0x45d9		/* jalr t9 */
@@ -1030,7 +1024,7 @@ static const bfd_vma mips_o32_exec_plt0_entry[] =
   0x8f990000,	/* lw $25, %lo(&GOTPLT[0])($28)				*/
   0x279c0000,	/* addiu $28, $28, %lo(&GOTPLT[0])			*/
   0x031cc023,	/* subu $24, $24, $28					*/
-  0x03e07821,	/* move $15, $31	# 32-bit move (addu)		*/
+  0x03e07825,	/* or t7, ra, zero					*/
   0x0018c082,	/* srl $24, $24, 2					*/
   0x0320f809,	/* jalr $25						*/
   0x2718fffe	/* subu $24, $24, 2					*/
@@ -1044,7 +1038,7 @@ static const bfd_vma mips_n32_exec_plt0_entry[] =
   0x8dd90000,	/* lw $25, %lo(&GOTPLT[0])($14)				*/
   0x25ce0000,	/* addiu $14, $14, %lo(&GOTPLT[0])			*/
   0x030ec023,	/* subu $24, $24, $14					*/
-  0x03e07821,	/* move $15, $31	# 32-bit move (addu)		*/
+  0x03e07825,	/* or t7, ra, zero					*/
   0x0018c082,	/* srl $24, $24, 2					*/
   0x0320f809,	/* jalr $25						*/
   0x2718fffe	/* subu $24, $24, 2					*/
@@ -1058,7 +1052,7 @@ static const bfd_vma mips_n64_exec_plt0_entry[] =
   0xddd90000,	/* ld $25, %lo(&GOTPLT[0])($14)				*/
   0x25ce0000,	/* addiu $14, $14, %lo(&GOTPLT[0])			*/
   0x030ec023,	/* subu $24, $24, $14					*/
-  0x03e0782d,	/* move $15, $31	# 64-bit move (daddu)		*/
+  0x03e07825,	/* or t7, ra, zero					*/
   0x0018c0c2,	/* srl $24, $24, 3					*/
   0x0320f809,	/* jalr $25						*/
   0x2718fffe	/* subu $24, $24, 2					*/
@@ -1091,7 +1085,7 @@ static const bfd_vma micromips_insn32_o32_exec_plt0_entry[] =
   0xff3c, 0x0000,	/* lw $25, %lo(&GOTPLT[0])($28)			*/
   0x339c, 0x0000,	/* addiu $28, $28, %lo(&GOTPLT[0])		*/
   0x0398, 0xc1d0,	/* subu $24, $24, $28				*/
-  0x001f, 0x7950,	/* move $15, $31				*/
+  0x001f, 0x7a90,	/* or $15, $31, zero				*/
   0x0318, 0x1040,	/* srl $24, $24, 2				*/
   0x03f9, 0x0f3c,	/* jalr $25					*/
   0x3318, 0xfffe	/* subu $24, $24, 2				*/
@@ -10714,8 +10708,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  if (htab->insn32)
 	    {
 	      bfd_put_micromips_32 (output_bfd,
-				    STUB_MOVE32_MICROMIPS (output_bfd),
-				    stub + idx);
+				    STUB_MOVE32_MICROMIPS, stub + idx);
 	      idx += 4;
 	    }
 	  else
@@ -10765,7 +10758,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  idx = 0;
 	  bfd_put_32 (output_bfd, STUB_LW (output_bfd), stub + idx);
 	  idx += 4;
-	  bfd_put_32 (output_bfd, STUB_MOVE (output_bfd), stub + idx);
+	  bfd_put_32 (output_bfd, STUB_MOVE, stub + idx);
 	  idx += 4;
 	  if (stub_size == stub_big_size)
 	    {
@@ -13224,8 +13217,8 @@ static const struct opcode_descriptor addiupc_insn =
 #define MOVE16_RS_FIELD(r) (((r) & 0x1f)     )
 
 static const struct opcode_descriptor move_insns_32[] = {
-  { /* "move",	"d,s",		*/ 0x00000150, 0xffe007ff }, /* addu d,s,$0 */
   { /* "move",	"d,s",		*/ 0x00000290, 0xffe007ff }, /* or   d,s,$0 */
+  { /* "move",	"d,s",		*/ 0x00000150, 0xffe007ff }, /* addu d,s,$0 */
   { 0, 0 }  /* End marker for find_match().  */
 };
 
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e483f4f..aea5508 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* config/tc-mips.c (move_register): Change to use 'or' only.
+	(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to
+	use or for move.
+
 2015-08-11  Jiong Wang  <jiong.wang@arm.com>
 
 	* config/tc-aarch64.c (reloc_table): New relocation modifiers
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index ecff88b..74b7fb4 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -9325,8 +9325,7 @@ move_register (int dest, int source)
       && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
     macro_build (NULL, "move", "mp,mj", dest, source);
   else
-    macro_build (NULL, GPR_SIZE == 32 ? "addu" : "daddu", "d,v,t",
-		 dest, source, 0);
+    macro_build (NULL, "or", "d,v,t", dest, source, 0);
 }
 
 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
@@ -15886,7 +15885,7 @@ s_cpload (int ignore ATTRIBUTE_UNUSED)
      daddu	$gp, $gp, $reg1
 
    If $reg2 is given, this results in:
-     daddu	$reg2, $gp, $0
+     or		$reg2, $gp, $0
      lui	$gp, %hi(%neg(%gp_rel(label)))
      addiu	$gp, $gp, %lo(%neg(%gp_rel(label)))
      daddu	$gp, $gp, $reg1
@@ -15966,8 +15965,7 @@ s_cpsetup (int ignore ATTRIBUTE_UNUSED)
 		   BFD_RELOC_LO16, SP);
     }
   else
-    macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
-		 mips_gp_register, 0);
+    move_register (mips_cpreturn_register, mips_gp_register);
 
   if (mips_in_shared || HAVE_64BIT_SYMBOLS)
     {
@@ -16080,7 +16078,7 @@ s_cprestore (int ignore ATTRIBUTE_UNUSED)
      ld		$gp, offset($sp)
 
    If a register $reg2 was given there, it results in:
-     daddu	$gp, $reg2, $0  */
+     or		$gp, $reg2, $0  */
 
 static void
 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
@@ -16118,8 +16116,8 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED)
       macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
     }
   else
-    macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
-		 mips_cpreturn_register, 0);
+    move_register (mips_gp_register, mips_cpreturn_register);
+
   macro_end ();
 
   mips_assembling_insn = FALSE;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 958bf71..f8ea3a2 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,42 @@
+2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* gas/mips/elf-rel23.d: Update test.
+	* gas/mips/elf-rel23.d: Ditto.
+	* gas/mips/elf-rel23a.d: Ditto.
+	* gas/mips/elf-rel23b.d: Ditto.
+	* gas/mips/elf_e_flags1.d: Ditto.
+	* gas/mips/elf_e_flags2.d: Ditto.
+	* gas/mips/elf_e_flags3.d: Ditto.
+	* gas/mips/elf_e_flags4.d: Ditto.
+	* gas/mips/loc-swap-dis.d: Ditto.
+	* gas/mips/micromips-insn32.d: Ditto.
+	* gas/mips/micromips-noinsn32.d: Ditto.
+	* gas/mips/micromips-trap.d: Ditto.
+	* gas/mips/micromips.d: Ditto.
+	* gas/mips/mips-abi32-pic.d: Ditto.
+	* gas/mips/mips-abi32.d: Ditto.
+	* gas/mips/mips-gp32-fp32-pic.d: Ditto.
+	* gas/mips/mips-gp32-fp32.d: Ditto.
+	* gas/mips/mips-gp32-fp64-pic.d: Ditto.
+	* gas/mips/mips-gp32-fp64.d: Ditto.
+	* gas/mips/mips-gp64-fp32-pic.d: Ditto.
+	* gas/mips/mips-gp64-fp32.d: Ditto.
+	* gas/mips/mips-gp64-fp64-pic.d: Ditto.
+	* gas/mips/mips-gp64-fp64.d: Ditto.
+	* gas/mips/mipsr6@loc-swap-dis.d: Ditto.
+	* gas/mips/tls-o32.d: Ditto.
+	* gas/mips/uld2-eb.d: Ditto.
+	* gas/mips/uld2-el.d: Ditto.
+	* gas/mips/ulw2-eb-ilocks.d: Ditto.
+	* gas/mips/ulw2-eb.d: Ditto.
+	* gas/mips/ulw2-el-ilocks.d: Ditto.
+	* gas/mips/ulw2-el.d: Ditto.
+	* gas/mips/move.d: New test.
+	* gas/mips/move.s: Ditto.
+	* gas/mips/micromips32-move.d: Ditto.
+	* gas/mips/micromips32-move.s: Ditto.
+	* gas/mips/mips.exp: Run the new tests.
+
 2015-08-11  Jiong Wang  <jiong.wang@arm.com>
 
 	* gas/aarch64/reloc-dtprel_lo12-1.s: New testcase.
diff --git a/gas/testsuite/gas/mips/elf-rel23.d b/gas/testsuite/gas/mips/elf-rel23.d
index 10b53ac..85cca8b 100644
--- a/gas/testsuite/gas/mips/elf-rel23.d
+++ b/gas/testsuite/gas/mips/elf-rel23.d
@@ -7,7 +7,7 @@
 Disassembly of section \.text:
 
 0+00 <.*>:
-.*:	0380282d 	move	\$5,\$28
+.*:	03802825 	move	\$5,\$28
 .*:	3c1c0000 	lui	\$28,0x0
 			.*: R_MIPS_GPREL16	foo
 			.*: R_MIPS_SUB	\*ABS\*
diff --git a/gas/testsuite/gas/mips/elf-rel23a.d b/gas/testsuite/gas/mips/elf-rel23a.d
index fb8737b..a3569e9 100644
--- a/gas/testsuite/gas/mips/elf-rel23a.d
+++ b/gas/testsuite/gas/mips/elf-rel23a.d
@@ -8,7 +8,7 @@
 Disassembly of section \.text:
 
 0+00 <.*>:
-.*:	0380282d 	move	\$5,\$28
+.*:	03802825 	move	\$5,\$28
 .*:	3c1c0000 	lui	\$28,0x0
 			.*: R_MIPS_GPREL16	foo
 			.*: R_MIPS_SUB	\*ABS\*
diff --git a/gas/testsuite/gas/mips/elf-rel23b.d b/gas/testsuite/gas/mips/elf-rel23b.d
index 88c9897..db9ba8a 100644
--- a/gas/testsuite/gas/mips/elf-rel23b.d
+++ b/gas/testsuite/gas/mips/elf-rel23b.d
@@ -8,7 +8,7 @@
 Disassembly of section \.text:
 
 0+00 <.*>:
-.*:	0380282d 	move	\$5,\$28
+.*:	03802825 	move	\$5,\$28
 .*:	3c1c0000 	lui	\$28,0x0
 			.*: R_MIPS_HI16	__gnu_local_gp
 .*:	279c0000 	addiu	\$28,\$28,0
diff --git a/gas/testsuite/gas/mips/elf_e_flags1.d b/gas/testsuite/gas/mips/elf_e_flags1.d
index cc5af56..71eb536 100644
--- a/gas/testsuite/gas/mips/elf_e_flags1.d
+++ b/gas/testsuite/gas/mips/elf_e_flags1.d
@@ -21,7 +21,7 @@ Disassembly of section .text:
   14:	afbf0020 	sw	ra,32\(sp\)
   18:	0c000000 	jal	0 <foo>
   1c:	00000000 	nop
-  20:	0000102[1d] 	move	v0,zero
+  20:	00001025 	move	v0,zero
   24:	8fbf0020 	lw	ra,32\(sp\)
   28:	00000000 	nop
   2c:	03e00008 	jr	ra
diff --git a/gas/testsuite/gas/mips/elf_e_flags2.d b/gas/testsuite/gas/mips/elf_e_flags2.d
index fceb547..c207e73 100644
--- a/gas/testsuite/gas/mips/elf_e_flags2.d
+++ b/gas/testsuite/gas/mips/elf_e_flags2.d
@@ -20,7 +20,7 @@ Disassembly of section .text:
   10:	afbf0020 	sw	ra,32\(sp\)
   14:	0c000000 	jal	0 <foo>
   18:	00000000 	nop
-  1c:	0000102[1d] 	move	v0,zero
+  1c:	00001025 	move	v0,zero
   20:	8fbf0020 	lw	ra,32\(sp\)
   24:	00000000 	nop
   28:	03e00008 	jr	ra
diff --git a/gas/testsuite/gas/mips/elf_e_flags3.d b/gas/testsuite/gas/mips/elf_e_flags3.d
index 4a72d98..bff2354 100644
--- a/gas/testsuite/gas/mips/elf_e_flags3.d
+++ b/gas/testsuite/gas/mips/elf_e_flags3.d
@@ -20,7 +20,7 @@ Disassembly of section .text:
   10:	afbf0020 	sw	ra,32\(sp\)
   14:	0c000000 	jal	0 <foo>
   18:	00000000 	nop
-  1c:	0000102[1d] 	move	v0,zero
+  1c:	00001025 	move	v0,zero
   20:	8fbf0020 	lw	ra,32\(sp\)
   24:	00000000 	nop
   28:	03e00008 	jr	ra
diff --git a/gas/testsuite/gas/mips/elf_e_flags4.d b/gas/testsuite/gas/mips/elf_e_flags4.d
index 4a72d98..bff2354 100644
--- a/gas/testsuite/gas/mips/elf_e_flags4.d
+++ b/gas/testsuite/gas/mips/elf_e_flags4.d
@@ -20,7 +20,7 @@ Disassembly of section .text:
   10:	afbf0020 	sw	ra,32\(sp\)
   14:	0c000000 	jal	0 <foo>
   18:	00000000 	nop
-  1c:	0000102[1d] 	move	v0,zero
+  1c:	00001025 	move	v0,zero
   20:	8fbf0020 	lw	ra,32\(sp\)
   24:	00000000 	nop
   28:	03e00008 	jr	ra
diff --git a/gas/testsuite/gas/mips/loc-swap-dis.d b/gas/testsuite/gas/mips/loc-swap-dis.d
index c4601b9..1137d53 100644
--- a/gas/testsuite/gas/mips/loc-swap-dis.d
+++ b/gas/testsuite/gas/mips/loc-swap-dis.d
@@ -8,26 +8,26 @@
 .*: +file format .*mips.*
 
 Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
 [0-9a-f]+ <[^>]*> 00800008 	jr	a0
 [0-9a-f]+ <[^>]*> 00000000 	nop
 [0-9a-f]+ <[^>]*> 00800008 	jr	a0
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 03e00008 	jr	ra
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 03e00008 	jr	ra
 [0-9a-f]+ <[^>]*> 00000000 	nop
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
 [0-9a-f]+ <[^>]*> 0080f809 	jalr	a0
 [0-9a-f]+ <[^>]*> 00000000 	nop
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 0080f809 	jalr	a0
 [0-9a-f]+ <[^>]*> 00000000 	nop
 [0-9a-f]+ <[^>]*> 0c000000 	jal	0+0000 <foo>
 [ 	]*[0-9a-f]+: R_MIPS_26	bar
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 0c000000 	jal	0+0000 <foo>
 [ 	]*[0-9a-f]+: R_MIPS_26	bar
 [0-9a-f]+ <[^>]*> 00000000 	nop
diff --git a/gas/testsuite/gas/mips/micromips-insn32.d b/gas/testsuite/gas/mips/micromips-insn32.d
index c0ff2db..a56b38f 100644
--- a/gas/testsuite/gas/mips/micromips-insn32.d
+++ b/gas/testsuite/gas/mips/micromips-insn32.d
@@ -75,35 +75,35 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	3040 ffff 	li	v0,-1
 [ 0-9a-f]+:	41a2 1234 	lui	v0,0x1234
 [ 0-9a-f]+:	5042 5678 	ori	v0,v0,0x5678
-[ 0-9a-f]+:	0016 0150 	move	zero,s6
-[ 0-9a-f]+:	0016 1150 	move	v0,s6
-[ 0-9a-f]+:	0016 1950 	move	v1,s6
-[ 0-9a-f]+:	0016 2150 	move	a0,s6
-[ 0-9a-f]+:	0016 2950 	move	a1,s6
-[ 0-9a-f]+:	0016 3150 	move	a2,s6
-[ 0-9a-f]+:	0016 3950 	move	a3,s6
-[ 0-9a-f]+:	0016 4150 	move	t0,s6
-[ 0-9a-f]+:	0016 4950 	move	t1,s6
-[ 0-9a-f]+:	0016 5150 	move	t2,s6
-[ 0-9a-f]+:	0016 f150 	move	s8,s6
-[ 0-9a-f]+:	0016 f950 	move	ra,s6
-[ 0-9a-f]+:	0000 0150 	move	zero,zero
-[ 0-9a-f]+:	0002 0150 	move	zero,v0
-[ 0-9a-f]+:	0003 0150 	move	zero,v1
-[ 0-9a-f]+:	0004 0150 	move	zero,a0
-[ 0-9a-f]+:	0005 0150 	move	zero,a1
-[ 0-9a-f]+:	0006 0150 	move	zero,a2
-[ 0-9a-f]+:	0007 0150 	move	zero,a3
-[ 0-9a-f]+:	0008 0150 	move	zero,t0
-[ 0-9a-f]+:	0009 0150 	move	zero,t1
-[ 0-9a-f]+:	000a 0150 	move	zero,t2
-[ 0-9a-f]+:	001e 0150 	move	zero,s8
-[ 0-9a-f]+:	001f 0150 	move	zero,ra
-[ 0-9a-f]+:	0002 b150 	move	s6,v0
-[ 0-9a-f]+:	0016 1150 	move	v0,s6
+[ 0-9a-f]+:	0016 0290 	move	zero,s6
+[ 0-9a-f]+:	0016 1290 	move	v0,s6
+[ 0-9a-f]+:	0016 1a90 	move	v1,s6
+[ 0-9a-f]+:	0016 2290 	move	a0,s6
+[ 0-9a-f]+:	0016 2a90 	move	a1,s6
+[ 0-9a-f]+:	0016 3290 	move	a2,s6
+[ 0-9a-f]+:	0016 3a90 	move	a3,s6
+[ 0-9a-f]+:	0016 4290 	move	t0,s6
+[ 0-9a-f]+:	0016 4a90 	move	t1,s6
+[ 0-9a-f]+:	0016 5290 	move	t2,s6
+[ 0-9a-f]+:	0016 f290 	move	s8,s6
+[ 0-9a-f]+:	0016 fa90 	move	ra,s6
+[ 0-9a-f]+:	0000 0290 	move	zero,zero
+[ 0-9a-f]+:	0002 0290 	move	zero,v0
+[ 0-9a-f]+:	0003 0290 	move	zero,v1
+[ 0-9a-f]+:	0004 0290 	move	zero,a0
+[ 0-9a-f]+:	0005 0290 	move	zero,a1
+[ 0-9a-f]+:	0006 0290 	move	zero,a2
+[ 0-9a-f]+:	0007 0290 	move	zero,a3
+[ 0-9a-f]+:	0008 0290 	move	zero,t0
+[ 0-9a-f]+:	0009 0290 	move	zero,t1
+[ 0-9a-f]+:	000a 0290 	move	zero,t2
+[ 0-9a-f]+:	001e 0290 	move	zero,s8
+[ 0-9a-f]+:	001f 0290 	move	zero,ra
+[ 0-9a-f]+:	0002 b290 	move	s6,v0
+[ 0-9a-f]+:	0016 1290 	move	v0,s6
 [ 0-9a-f]+:	9400 fffe 	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	test
-[ 0-9a-f]+:	0002 b150 	move	s6,v0
+[ 0-9a-f]+:	0002 b290 	move	s6,v0
 [ 0-9a-f]+:	9400 fffe 	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	test
 [ 0-9a-f]+:	0000 0000 	nop
@@ -123,13 +123,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	0000 0000 	nop
 [ 0-9a-f]+:	4043 fffe 	bgez	v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	.*
-[ 0-9a-f]+:	0003 1150 	move	v0,v1
+[ 0-9a-f]+:	0003 1290 	move	v0,v1
 [ 0-9a-f]+:	0060 1190 	neg	v0,v1
 
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	4044 fffe 	bgez	a0,[0-9a-f]+ <.*>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	.*
-[ 0-9a-f]+:	0004 1150 	move	v0,a0
+[ 0-9a-f]+:	0004 1290 	move	v0,a0
 [ 0-9a-f]+:	0080 1190 	neg	v0,a0
 
 [0-9a-f]+ <.*>:
@@ -894,7 +894,7 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0002 1d7c 	mflo	v0
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	0004 1950 	move	v1,a0
+[ 0-9a-f]+:	0004 1a90 	move	v1,a0
 [ 0-9a-f]+:	0080 1990 	neg	v1,a0
 [ 0-9a-f]+:	3020 0002 	li	at,2
 [ 0-9a-f]+:	0024 ab3c 	div	zero,a0,at
@@ -918,7 +918,7 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0002 1d7c 	mflo	v0
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	0004 1950 	move	v1,a0
+[ 0-9a-f]+:	0004 1a90 	move	v1,a0
 [ 0-9a-f]+:	3020 ffff 	li	at,-1
 [ 0-9a-f]+:	0024 bb3c 	divu	zero,a0,at
 [ 0-9a-f]+:	0003 1d7c 	mflo	v1
@@ -2270,8 +2270,8 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0002 0d7c 	mfhi	v0
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	0000 1950 	move	v1,zero
-[ 0-9a-f]+:	0000 1950 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
 [ 0-9a-f]+:	3020 0002 	li	at,2
 [ 0-9a-f]+:	0024 ab3c 	div	zero,a0,at
 [ 0-9a-f]+:	0003 0d7c 	mfhi	v1
@@ -2306,7 +2306,7 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0002 0d7c 	mfhi	v0
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	0000 1950 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
 [ 0-9a-f]+:	3020 ffff 	li	at,-1
 [ 0-9a-f]+:	0024 bb3c 	divu	zero,a0,at
 [ 0-9a-f]+:	0003 0d7c 	mfhi	v1
@@ -6456,7 +6456,7 @@ Disassembly of section \.text:
 [0-9a-f]+ <test_mips64>:
 [ 0-9a-f]+:	4043 fffe 	bgez	v1,[0-9a-f]+ <test_mips64>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	.*
-[ 0-9a-f]+:	5803 1150 	move	v0,v1
+[ 0-9a-f]+:	0003 1290 	move	v0,v1
 [ 0-9a-f]+:	5860 1190 	dneg	v0,v1
 
 [0-9a-f]+ <.*>:
@@ -6555,7 +6555,7 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0002 1d7c 	mflo	v0
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	5804 1950 	move	v1,a0
+[ 0-9a-f]+:	0004 1a90 	move	v1,a0
 [ 0-9a-f]+:	5880 1990 	dneg	v1,a0
 [ 0-9a-f]+:	3020 0002 	li	at,2
 [ 0-9a-f]+:	5824 ab3c 	ddiv	zero,a0,at
@@ -6579,7 +6579,7 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0002 1d7c 	mflo	v0
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	5804 1950 	move	v1,a0
+[ 0-9a-f]+:	0004 1a90 	move	v1,a0
 [ 0-9a-f]+:	3020 ffff 	li	at,-1
 [ 0-9a-f]+:	5824 bb3c 	ddivu	zero,a0,at
 [ 0-9a-f]+:	0003 1d7c 	mflo	v1
@@ -6966,8 +6966,8 @@ Disassembly of section \.text:
 
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	5800 1950 	move	v1,zero
-[ 0-9a-f]+:	5800 1950 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
 [ 0-9a-f]+:	3020 0002 	li	at,2
 [ 0-9a-f]+:	5824 ab3c 	ddiv	zero,a0,at
 [ 0-9a-f]+:	0003 0d7c 	mfhi	v1
@@ -7010,8 +7010,8 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0000 0d7c 	mfhi	zero
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	5800 1950 	move	v1,zero
-[ 0-9a-f]+:	5800 1950 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
 [ 0-9a-f]+:	3020 0002 	li	at,2
 [ 0-9a-f]+:	5824 ab3c 	ddiv	zero,a0,at
 [ 0-9a-f]+:	0003 0d7c 	mfhi	v1
@@ -7032,7 +7032,7 @@ Disassembly of section \.text:
 [0-9a-f]+ <.*>:
 [ 0-9a-f]+:	0000 0d7c 	mfhi	zero
 [ 0-9a-f]+:	0007 0007 	break	0x7
-[ 0-9a-f]+:	5800 1950 	move	v1,zero
+[ 0-9a-f]+:	0000 1a90 	move	v1,zero
 [ 0-9a-f]+:	3020 ffff 	li	at,-1
 [ 0-9a-f]+:	5824 bb3c 	ddivu	zero,a0,at
 [ 0-9a-f]+:	0003 0d7c 	mfhi	v1
@@ -7673,50 +7673,50 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	78c0 0000 	addiu	s1,\$pc,-16777216
 
 [0-9a-f]+ <test_spec107>:
-[ 0-9a-f]+:	5800 2950 	move	a1,zero
-[ 0-9a-f]+:	5800 3150 	move	a2,zero
-[ 0-9a-f]+:	5800 2950 	move	a1,zero
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5800 3150 	move	a2,zero
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5800 2150 	move	a0,zero
-[ 0-9a-f]+:	5800 a950 	move	s5,zero
-[ 0-9a-f]+:	5800 2150 	move	a0,zero
-[ 0-9a-f]+:	5800 b150 	move	s6,zero
-[ 0-9a-f]+:	5800 2150 	move	a0,zero
-[ 0-9a-f]+:	5800 2950 	move	a1,zero
-[ 0-9a-f]+:	5800 2150 	move	a0,zero
-[ 0-9a-f]+:	5800 3150 	move	a2,zero
-[ 0-9a-f]+:	5800 2150 	move	a0,zero
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5811 2150 	move	a0,s1
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5802 2150 	move	a0,v0
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5803 2150 	move	a0,v1
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5810 2150 	move	a0,s0
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5812 2150 	move	a0,s2
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5813 2150 	move	a0,s3
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5800 3950 	move	a3,zero
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5811 3950 	move	a3,s1
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5802 3950 	move	a3,v0
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5803 3950 	move	a3,v1
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5810 3950 	move	a3,s0
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5812 3950 	move	a3,s2
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5813 3950 	move	a3,s3
-[ 0-9a-f]+:	5814 2150 	move	a0,s4
-[ 0-9a-f]+:	5814 3950 	move	a3,s4
+[ 0-9a-f]+:	0000 2a90 	move	a1,zero
+[ 0-9a-f]+:	0000 3290 	move	a2,zero
+[ 0-9a-f]+:	0000 2a90 	move	a1,zero
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0000 3290 	move	a2,zero
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0000 2290 	move	a0,zero
+[ 0-9a-f]+:	0000 aa90 	move	s5,zero
+[ 0-9a-f]+:	0000 2290 	move	a0,zero
+[ 0-9a-f]+:	0000 b290 	move	s6,zero
+[ 0-9a-f]+:	0000 2290 	move	a0,zero
+[ 0-9a-f]+:	0000 2a90 	move	a1,zero
+[ 0-9a-f]+:	0000 2290 	move	a0,zero
+[ 0-9a-f]+:	0000 3290 	move	a2,zero
+[ 0-9a-f]+:	0000 2290 	move	a0,zero
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0011 2290 	move	a0,s1
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0002 2290 	move	a0,v0
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0003 2290 	move	a0,v1
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0010 2290 	move	a0,s0
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0012 2290 	move	a0,s2
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0013 2290 	move	a0,s3
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0000 3a90 	move	a3,zero
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0011 3a90 	move	a3,s1
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0002 3a90 	move	a3,v0
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0003 3a90 	move	a3,v1
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0010 3a90 	move	a3,s0
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0012 3a90 	move	a3,s2
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0013 3a90 	move	a3,s3
+[ 0-9a-f]+:	0014 2290 	move	a0,s4
+[ 0-9a-f]+:	0014 3a90 	move	a3,s4
 [ 0-9a-f]+:	4060 fffe 	bal	[0-9a-f]+ <.*\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	test_spec107
 [ 0-9a-f]+:	0000 0000 	nop
diff --git a/gas/testsuite/gas/mips/micromips-noinsn32.d b/gas/testsuite/gas/mips/micromips-noinsn32.d
index 5bbaab1..3b4a795 100644
--- a/gas/testsuite/gas/mips/micromips-noinsn32.d
+++ b/gas/testsuite/gas/mips/micromips-noinsn32.d
@@ -100,10 +100,10 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	0c1e      	move	zero,s8
 [ 0-9a-f]+:	0c1f      	move	zero,ra
 [ 0-9a-f]+:	0ec2      	move	s6,v0
-[ 0-9a-f]+:	0016 1150 	move	v0,s6
+[ 0-9a-f]+:	0016 1290 	move	v0,s6
 [ 0-9a-f]+:	cfff      	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC10_S1	test
-[ 0-9a-f]+:	0002 b150 	move	s6,v0
+[ 0-9a-f]+:	0002 b290 	move	s6,v0
 [ 0-9a-f]+:	9400 fffe 	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC16_S1	test
 [ 0-9a-f]+:	0c00      	nop
diff --git a/gas/testsuite/gas/mips/micromips-trap.d b/gas/testsuite/gas/mips/micromips-trap.d
index cfb0979..8f33d9b 100644
--- a/gas/testsuite/gas/mips/micromips-trap.d
+++ b/gas/testsuite/gas/mips/micromips-trap.d
@@ -103,10 +103,10 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	0ec2      	move	s6,v0
 [ 0-9a-f]+:	0c56      	move	v0,s6
 [ 0-9a-f]+:	0ec2      	move	s6,v0
-[ 0-9a-f]+:	0016 1150 	move	v0,s6
+[ 0-9a-f]+:	0016 1290 	move	v0,s6
 [ 0-9a-f]+:	cfff      	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC10_S1	test
-[ 0-9a-f]+:	0002 b150 	move	s6,v0
+[ 0-9a-f]+:	0002 b290 	move	s6,v0
 [ 0-9a-f]+:	cfff      	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC10_S1	test
 [ 0-9a-f]+:	0c00      	nop
diff --git a/gas/testsuite/gas/mips/micromips.d b/gas/testsuite/gas/mips/micromips.d
index e262663..8801c56 100644
--- a/gas/testsuite/gas/mips/micromips.d
+++ b/gas/testsuite/gas/mips/micromips.d
@@ -103,10 +103,10 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	0ec2      	move	s6,v0
 [ 0-9a-f]+:	0c56      	move	v0,s6
 [ 0-9a-f]+:	0ec2      	move	s6,v0
-[ 0-9a-f]+:	0016 1150 	move	v0,s6
+[ 0-9a-f]+:	0016 1290 	move	v0,s6
 [ 0-9a-f]+:	cfff      	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC10_S1	test
-[ 0-9a-f]+:	0002 b150 	move	s6,v0
+[ 0-9a-f]+:	0002 b290 	move	s6,v0
 [ 0-9a-f]+:	cfff      	b	[0-9a-f]+ <test\+0x[0-9a-f]+>
 [ 	]*[0-9a-f]+: R_MICROMIPS_PC10_S1	test
 [ 0-9a-f]+:	0c00      	nop
diff --git a/gas/testsuite/gas/mips/micromips32-move.d b/gas/testsuite/gas/mips/micromips32-move.d
new file mode 100644
index 0000000..1a30f06
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips32-move.d
@@ -0,0 +1,14 @@
+#objdump: -dr -m mips:micromips
+#name: microMIPS insn32 move test
+#source: micromips32-move.s
+
+# Check objdump's disassembly of the move menomic for addu, daddu and or.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+ <.*>:
+   0:	001f 6a90 	move	t5,ra
+   4:	001f 6950 	move	t5,ra
+   8:	581f 6950 	move	t5,ra
+   c:	001f 6a90 	move	t5,ra
diff --git a/gas/testsuite/gas/mips/micromips32-move.s b/gas/testsuite/gas/mips/micromips32-move.s
new file mode 100644
index 0000000..a94cfe4
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips32-move.s
@@ -0,0 +1,6 @@
+	.set	micromips
+	.set	insn32
+	move	$13, $31
+	addu	$13, $31, $0
+	daddu	$13, $31, $0
+	or	$13, $31, $0
diff --git a/gas/testsuite/gas/mips/mips-abi32-pic.d b/gas/testsuite/gas/mips/mips-abi32-pic.d
index fd18bf8..94f2acc 100644
--- a/gas/testsuite/gas/mips/mips-abi32-pic.d
+++ b/gas/testsuite/gas/mips/mips-abi32-pic.d
@@ -80,7 +80,7 @@ Disassembly of section .text:
  118:	a8240000 	swl	a0,0\(at\)
  11c:	b8240003 	swr	a0,3\(at\)
  120:	3c043ff0 	lui	a0,0x3ff0
- 124:	00002821 	move	a1,zero
+ 124:	00002825 	move	a1,zero
  128:	8f810000 	lw	at,0\(gp\)
  12c:	8c240000 	lw	a0,0\(at\)
  130:	8c250004 	lw	a1,4\(at\)
@@ -93,7 +93,7 @@ Disassembly of section .text:
  14c:	2c840001 	sltiu	a0,a0,1
  150:	24a40064 	addiu	a0,a1,100
  154:	0004202b 	sltu	a0,zero,a0
- 158:	00a02021 	move	a0,a1
+ 158:	00a02025 	move	a0,a1
 
 0+015c <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-abi32.d b/gas/testsuite/gas/mips/mips-abi32.d
index 51ab40c..0907b84 100644
--- a/gas/testsuite/gas/mips/mips-abi32.d
+++ b/gas/testsuite/gas/mips/mips-abi32.d
@@ -60,7 +60,7 @@ Disassembly of section .text:
   c8:	a8240000 	swl	a0,0\(at\)
   cc:	b8240003 	swr	a0,3\(at\)
   d0:	3c043ff0 	lui	a0,0x3ff0
-  d4:	00002821 	move	a1,zero
+  d4:	00002825 	move	a1,zero
   d8:	3c010000 	lui	at,0x0
   dc:	8c240000 	lw	a0,0\(at\)
   e0:	8c250004 	lw	a1,4\(at\)
@@ -72,7 +72,7 @@ Disassembly of section .text:
   f8:	2c840001 	sltiu	a0,a0,1
   fc:	24a40064 	addiu	a0,a1,100
  100:	0004202b 	sltu	a0,zero,a0
- 104:	00a02021 	move	a0,a1
+ 104:	00a02025 	move	a0,a1
 
 0+0108 <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d b/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
index 3fb84e9..73b0178 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
@@ -80,7 +80,7 @@ Disassembly of section .text:
  118:	a8240000 	swl	a0,0\(at\)
  11c:	b8240003 	swr	a0,3\(at\)
  120:	3c043ff0 	lui	a0,0x3ff0
- 124:	00002821 	move	a1,zero
+ 124:	00002825 	move	a1,zero
  128:	8f810000 	lw	at,0\(gp\)
  12c:	8c240000 	lw	a0,0\(at\)
  130:	8c250004 	lw	a1,4\(at\)
@@ -93,7 +93,7 @@ Disassembly of section .text:
  14c:	2c840001 	sltiu	a0,a0,1
  150:	24a40064 	addiu	a0,a1,100
  154:	0004202b 	sltu	a0,zero,a0
- 158:	00a02021 	move	a0,a1
+ 158:	00a02025 	move	a0,a1
 
 0+015c <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp32.d b/gas/testsuite/gas/mips/mips-gp32-fp32.d
index 82e3828..5cd8f70 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp32.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp32.d
@@ -60,7 +60,7 @@ Disassembly of section .text:
   c8:	a8240000 	swl	a0,0\(at\)
   cc:	b8240003 	swr	a0,3\(at\)
   d0:	3c043ff0 	lui	a0,0x3ff0
-  d4:	00002821 	move	a1,zero
+  d4:	00002825 	move	a1,zero
   d8:	3c010000 	lui	at,0x0
   dc:	8c240000 	lw	a0,0\(at\)
   e0:	8c250004 	lw	a1,4\(at\)
@@ -72,7 +72,7 @@ Disassembly of section .text:
   f8:	2c840001 	sltiu	a0,a0,1
   fc:	24a40064 	addiu	a0,a1,100
  100:	0004202b 	sltu	a0,zero,a0
- 104:	00a02021 	move	a0,a1
+ 104:	00a02025 	move	a0,a1
 
 0+0108 <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
index 3ebbe3f..1e4606c 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
@@ -81,7 +81,7 @@ Disassembly of section .text:
  118:	a8240000 	swl	a0,0\(at\)
  11c:	b8240003 	swr	a0,3\(at\)
  120:	3c043ff0 	lui	a0,0x3ff0
- 124:	00002821 	move	a1,zero
+ 124:	00002825 	move	a1,zero
  128:	8f810000 	lw	at,0\(gp\)
  12c:	8c240000 	lw	a0,0\(at\)
  130:	8c250004 	lw	a1,4\(at\)
@@ -93,7 +93,7 @@ Disassembly of section .text:
  148:	2c840001 	sltiu	a0,a0,1
  14c:	24a40064 	addiu	a0,a1,100
  150:	0004202b 	sltu	a0,zero,a0
- 154:	00a02021 	move	a0,a1
+ 154:	00a02025 	move	a0,a1
  158:	46231040 	add.d	\$f1,\$f2,\$f3
 
 0+015c <[^>]*>:
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64.d b/gas/testsuite/gas/mips/mips-gp32-fp64.d
index 2181bb1..6d0b19e 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp64.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp64.d
@@ -61,7 +61,7 @@ Disassembly of section .text:
   c8:	a8240000 	swl	a0,0\(at\)
   cc:	b8240003 	swr	a0,3\(at\)
   d0:	3c043ff0 	lui	a0,0x3ff0
-  d4:	00002821 	move	a1,zero
+  d4:	00002825 	move	a1,zero
   d8:	3c010000 	lui	at,0x0
   dc:	8c240000 	lw	a0,0\(at\)
   e0:	8c250004 	lw	a1,4\(at\)
@@ -71,7 +71,7 @@ Disassembly of section .text:
   f0:	2c840001 	sltiu	a0,a0,1
   f4:	24a40064 	addiu	a0,a1,100
   f8:	0004202b 	sltu	a0,zero,a0
-  fc:	00a02021 	move	a0,a1
+  fc:	00a02025 	move	a0,a1
  100:	46231040 	add.d	\$f1,\$f2,\$f3
 
 0+0104 <[^>]*>:
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
index 52fe8af..d83d7f9 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
@@ -93,7 +93,7 @@ Disassembly of section .text:
  148:	2c840001 	sltiu	a0,a0,1
  14c:	64a40064 	daddiu	a0,a1,100
  150:	0004202b 	sltu	a0,zero,a0
- 154:	00a0202d 	move	a0,a1
+ 154:	00a02025 	move	a0,a1
  158:	8f840000 	lw	a0,0\(gp\)
  15c:	24840000 	addiu	a0,a0,0
  160:	8f840000 	lw	a0,0\(gp\)
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32.d b/gas/testsuite/gas/mips/mips-gp64-fp32.d
index 9f7540b..035cfd6 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp32.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp32.d
@@ -67,7 +67,7 @@ Disassembly of section .text:
   e0:	2c840001 	sltiu	a0,a0,1
   e4:	64a40064 	daddiu	a0,a1,100
   e8:	0004202b 	sltu	a0,zero,a0
-  ec:	00a0202d 	move	a0,a1
+  ec:	00a02025 	move	a0,a1
   f0:	27840000 	addiu	a0,gp,0
   f4:	3c040000 	lui	a0,0x0
   f8:	24840000 	addiu	a0,a0,0
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d b/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
index 2e37f68..b66f983 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
@@ -92,7 +92,7 @@ Disassembly of section .text:
  148:	2c840001 	sltiu	a0,a0,1
  14c:	64a40064 	daddiu	a0,a1,100
  150:	0004202b 	sltu	a0,zero,a0
- 154:	00a0202d 	move	a0,a1
+ 154:	00a02025 	move	a0,a1
  158:	8f840000 	lw	a0,0\(gp\)
  15c:	24840000 	addiu	a0,a0,0
  160:	8f840000 	lw	a0,0\(gp\)
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp64.d b/gas/testsuite/gas/mips/mips-gp64-fp64.d
index 5cd5028..f5fe15f 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp64.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp64.d
@@ -67,7 +67,7 @@ Disassembly of section .text:
   e0:	2c840001 	sltiu	a0,a0,1
   e4:	64a40064 	daddiu	a0,a1,100
   e8:	0004202b 	sltu	a0,zero,a0
-  ec:	00a0202d 	move	a0,a1
+  ec:	00a02025 	move	a0,a1
   f0:	27840000 	addiu	a0,gp,0
   f4:	3c040000 	lui	a0,0x0
   f8:	24840000 	addiu	a0,a0,0
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 4568f24..74e0a79 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1022,6 +1022,10 @@ if { [istarget mips*-*-vxworks*] } {
 	run_dump_test "n32-consec"
     }
 
+    # tests of objdump's ability to disassemble the move mnemonic
+    run_dump_test_arches "move"	[mips_arch_list_matching mips64 !micromips]
+    run_dump_test_arches "micromips32-move" [mips_arch_list_matching micromips]
+
     # tests of objdump's ability to disassemble using different
     # register names.
     run_dump_test "gpr-names-numeric"
diff --git a/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d b/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d
index d377f6a..caee888 100644
--- a/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d
+++ b/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d
@@ -8,26 +8,26 @@
 .*: +file format .*mips.*
 
 Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
 [0-9a-f]+ <[^>]*> 00800009 	jr	a0
 [0-9a-f]+ <[^>]*> 00000000 	nop
 [0-9a-f]+ <[^>]*> 00800009 	jr	a0
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 03e00009 	jr	ra
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 03e00009 	jr	ra
 [0-9a-f]+ <[^>]*> 00000000 	nop
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
 [0-9a-f]+ <[^>]*> 0080f809 	jalr	a0
 [0-9a-f]+ <[^>]*> 00000000 	nop
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 0080f809 	jalr	a0
 [0-9a-f]+ <[^>]*> 00000000 	nop
 [0-9a-f]+ <[^>]*> 0c000000 	jal	0+0000 <foo>
 [ 	]*[0-9a-f]+: R_MIPS_26	bar
-[0-9a-f]+ <[^>]*> 02002021 	move	a0,s0
-[0-9a-f]+ <[^>]*> 0200f821 	move	ra,s0
+[0-9a-f]+ <[^>]*> 02002025 	move	a0,s0
+[0-9a-f]+ <[^>]*> 0200f825 	move	ra,s0
 [0-9a-f]+ <[^>]*> 0c000000 	jal	0+0000 <foo>
 [ 	]*[0-9a-f]+: R_MIPS_26	bar
 [0-9a-f]+ <[^>]*> 00000000 	nop
diff --git a/gas/testsuite/gas/mips/move.d b/gas/testsuite/gas/mips/move.d
new file mode 100644
index 0000000..aa978ea
--- /dev/null
+++ b/gas/testsuite/gas/mips/move.d
@@ -0,0 +1,14 @@
+#objdump: -dr
+#name: MIPS move disassembly test
+#source: move.s
+
+# Check objdump's disassembly of the move menomic for addu, daddu and or.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+ <.*>:
+   0:	03e06825 	move	t5,ra
+   4:	03e06821 	move	t5,ra
+   8:	03e0682d 	move	t5,ra
+   c:	03e06825 	move	t5,ra
diff --git a/gas/testsuite/gas/mips/move.s b/gas/testsuite/gas/mips/move.s
new file mode 100644
index 0000000..912577b
--- /dev/null
+++ b/gas/testsuite/gas/mips/move.s
@@ -0,0 +1,4 @@
+	move	$13, $31
+	addu	$13, $31, $0
+	daddu	$13, $31, $0
+	or	$13, $31, $0
diff --git a/gas/testsuite/gas/mips/tls-o32.d b/gas/testsuite/gas/mips/tls-o32.d
index d81ba4e..32f27af 100644
--- a/gas/testsuite/gas/mips/tls-o32.d
+++ b/gas/testsuite/gas/mips/tls-o32.d
@@ -14,7 +14,7 @@ Disassembly of section .text:
    8:	0399e021 	addu	gp,gp,t9
    c:	27bdfff0 	addiu	sp,sp,-16
   10:	afbe0008 	sw	s8,8\(sp\)
-  14:	03a0f021 	move	s8,sp
+  14:	03a0f025 	move	s8,sp
   18:	afbc0000 	sw	gp,0\(sp\)
   1c:	8f990000 	lw	t9,0\(gp\)
 			1c: R_MIPS_CALL16	__tls_get_addr
@@ -31,7 +31,7 @@ Disassembly of section .text:
   3c:	0320f809 	jalr	t9
   40:	00000000 	nop
   44:	8fdc0000 	lw	gp,0\(s8\)
-  48:	00401021 	move	v0,v0
+  48:	00401025 	move	v0,v0
   4c:	3c030000 	lui	v1,0x0
 			4c: R_MIPS_TLS_DTPREL_HI16	tlsvar_ld
   50:	24630000 	addiu	v1,v1,0
@@ -48,7 +48,7 @@ Disassembly of section .text:
   70:	34630000 	ori	v1,v1,0x0
 			70: R_MIPS_TLS_TPREL_LO16	tlsvar_le
   74:	00621821 	addu	v1,v1,v0
-  78:	03c0e821 	move	sp,s8
+  78:	03c0e825 	move	sp,s8
   7c:	8fbe0008 	lw	s8,8\(sp\)
   80:	03e00008 	jr	ra
   84:	27bd0010 	addiu	sp,sp,16
diff --git a/gas/testsuite/gas/mips/uld2-eb.d b/gas/testsuite/gas/mips/uld2-eb.d
index 8a4d37c..da72fca 100644
--- a/gas/testsuite/gas/mips/uld2-eb.d
+++ b/gas/testsuite/gas/mips/uld2-eb.d
@@ -4,10 +4,6 @@
 #source: uld2.s
 
 # Further checks of uld macro.
-# XXX: note: when 'move' is changed to use 'or' rather than daddu, the
-# XXX: 'move' opcodes shown here (whose raw instruction fields are daddu)
-# XXX: should be changed to be 'or' instructions and this comment should be
-# XXX: removed.
 
 .*: +file format .*mips.*
 
@@ -18,8 +14,8 @@ Disassembly of section .text:
 0+000c <[^>]*> 6ca40008 	ldr	\$4,8\(\$5\)
 0+0010 <[^>]*> 68a10000 	ldl	\$1,0\(\$5\)
 0+0014 <[^>]*> 6ca10007 	ldr	\$1,7\(\$5\)
-0+0018 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0018 <[^>]*> 00202825 	move	\$5,\$1
 0+001c <[^>]*> 68a10001 	ldl	\$1,1\(\$5\)
 0+0020 <[^>]*> 6ca10008 	ldr	\$1,8\(\$5\)
-0+0024 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0024 <[^>]*> 00202825 	move	\$5,\$1
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/uld2-el.d b/gas/testsuite/gas/mips/uld2-el.d
index e932f35..c77c228 100644
--- a/gas/testsuite/gas/mips/uld2-el.d
+++ b/gas/testsuite/gas/mips/uld2-el.d
@@ -4,10 +4,6 @@
 #source: uld2.s
 
 # Further checks of uld macro.
-# XXX: note: when 'move' is changed to use 'or' rather than daddu, the
-# XXX: 'move' opcodes shown here (whose raw instruction fields are daddu)
-# XXX: should be changed to be 'or' instructions and this comment should be
-# XXX: removed.
 
 .*: +file format .*mips.*
 
@@ -18,8 +14,8 @@ Disassembly of section .text:
 0+000c <[^>]*> 6ca40001 	ldr	\$4,1\(\$5\)
 0+0010 <[^>]*> 68a10007 	ldl	\$1,7\(\$5\)
 0+0014 <[^>]*> 6ca10000 	ldr	\$1,0\(\$5\)
-0+0018 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0018 <[^>]*> 00202825 	move	\$5,\$1
 0+001c <[^>]*> 68a10008 	ldl	\$1,8\(\$5\)
 0+0020 <[^>]*> 6ca10001 	ldr	\$1,1\(\$5\)
-0+0024 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0024 <[^>]*> 00202825 	move	\$5,\$1
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ulw2-eb-ilocks.d b/gas/testsuite/gas/mips/ulw2-eb-ilocks.d
index f967aa2..a1a71ab 100644
--- a/gas/testsuite/gas/mips/ulw2-eb-ilocks.d
+++ b/gas/testsuite/gas/mips/ulw2-eb-ilocks.d
@@ -4,10 +4,6 @@
 #source: ulw2.s
 
 # Further checks of ulw macro.
-# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
-# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
-# XXX: should be changed to be 'or' instructions and this comment should be
-# XXX: removed.
 
 .*: +file format .*mips.*
 
@@ -18,8 +14,8 @@ Disassembly of section .text:
 0+000c <[^>]*> 98a40004 	lwr	\$4,4\(\$5\)
 0+0010 <[^>]*> 88a10000 	lwl	\$1,0\(\$5\)
 0+0014 <[^>]*> 98a10003 	lwr	\$1,3\(\$5\)
-0+0018 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0018 <[^>]*> 00202825 	move	\$5,\$1
 0+001c <[^>]*> 88a10001 	lwl	\$1,1\(\$5\)
 0+0020 <[^>]*> 98a10004 	lwr	\$1,4\(\$5\)
-0+0024 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0024 <[^>]*> 00202825 	move	\$5,\$1
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ulw2-eb.d b/gas/testsuite/gas/mips/ulw2-eb.d
index 9341369..e261250 100644
--- a/gas/testsuite/gas/mips/ulw2-eb.d
+++ b/gas/testsuite/gas/mips/ulw2-eb.d
@@ -4,10 +4,6 @@
 #source: ulw2.s
 
 # Further checks of ulw macro.
-# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
-# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
-# XXX: should be changed to be 'or' instructions and this comment should be
-# XXX: removed.
 
 .*: +file format .*mips.*
 
@@ -19,9 +15,9 @@ Disassembly of section .text:
 0+0010 <[^>]*> 88a10000 	lwl	\$1,0\(\$5\)
 0+0014 <[^>]*> 98a10003 	lwr	\$1,3\(\$5\)
 0+0018 <[^>]*> 00000000 	nop
-0+001c <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+001c <[^>]*> 00202825 	move	\$5,\$1
 0+0020 <[^>]*> 88a10001 	lwl	\$1,1\(\$5\)
 0+0024 <[^>]*> 98a10004 	lwr	\$1,4\(\$5\)
 0+0028 <[^>]*> 00000000 	nop
-0+002c <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+002c <[^>]*> 00202825 	move	\$5,\$1
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ulw2-el-ilocks.d b/gas/testsuite/gas/mips/ulw2-el-ilocks.d
index 5e08cef..c21cfcb 100644
--- a/gas/testsuite/gas/mips/ulw2-el-ilocks.d
+++ b/gas/testsuite/gas/mips/ulw2-el-ilocks.d
@@ -4,10 +4,6 @@
 #source: ulw2.s
 
 # Further checks of ulw macro.
-# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
-# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
-# XXX: should be changed to be 'or' instructions and this comment should be
-# XXX: removed.
 
 .*: +file format .*mips.*
 
@@ -18,8 +14,8 @@ Disassembly of section .text:
 0+000c <[^>]*> 98a40001 	lwr	\$4,1\(\$5\)
 0+0010 <[^>]*> 88a10003 	lwl	\$1,3\(\$5\)
 0+0014 <[^>]*> 98a10000 	lwr	\$1,0\(\$5\)
-0+0018 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0018 <[^>]*> 00202825 	move	\$5,\$1
 0+001c <[^>]*> 88a10004 	lwl	\$1,4\(\$5\)
 0+0020 <[^>]*> 98a10001 	lwr	\$1,1\(\$5\)
-0+0024 <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+0024 <[^>]*> 00202825 	move	\$5,\$1
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ulw2-el.d b/gas/testsuite/gas/mips/ulw2-el.d
index 75bf408..5981bc8 100644
--- a/gas/testsuite/gas/mips/ulw2-el.d
+++ b/gas/testsuite/gas/mips/ulw2-el.d
@@ -4,11 +4,6 @@
 #source: ulw2.s
 
 # Further checks of ulw macro.
-# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
-# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
-# XXX: should be changed to be 'or' instructions and this comment should be
-# XXX: removed.
-
 .*: +file format .*mips.*
 
 Disassembly of section .text:
@@ -19,9 +14,9 @@ Disassembly of section .text:
 0+0010 <[^>]*> 88a10003 	lwl	\$1,3\(\$5\)
 0+0014 <[^>]*> 98a10000 	lwr	\$1,0\(\$5\)
 0+0018 <[^>]*> 00000000 	nop
-0+001c <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+001c <[^>]*> 00202825 	move	\$5,\$1
 0+0020 <[^>]*> 88a10004 	lwl	\$1,4\(\$5\)
 0+0024 <[^>]*> 98a10001 	lwr	\$1,1\(\$5\)
 0+0028 <[^>]*> 00000000 	nop
-0+002c <[^>]*> 0020282[1d] 	move	\$5,\$1
+0+002c <[^>]*> 00202825 	move	\$5,\$1
 	\.\.\.
diff --git a/gold/ChangeLog b/gold/ChangeLog
index 0012445..0c5a40c 100644
--- a/gold/ChangeLog
+++ b/gold/ChangeLog
@@ -1,3 +1,13 @@
+2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64,
+	lazy_stub_normal_1, lazy_stub_normal_1_n64,
+	lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big,
+	lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64,
+	lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big,
+	lazy_stub_micromips32_big_n64): Update to use 'or' for move instead
+	of 'addu/daddu'.
+
 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* configure: Regenerated.
diff --git a/gold/mips.cc b/gold/mips.cc
index acf76cf..01cf33f 100644
--- a/gold/mips.cc
+++ b/gold/mips.cc
@@ -6162,7 +6162,7 @@ const uint32_t Mips_output_data_plt<size, big_endian>::plt0_entry_o32[] =
   0x8f990000,         // lw $25, %lo(&GOTPLT[0])($28)
   0x279c0000,         // addiu $28, $28, %lo(&GOTPLT[0])
   0x031cc023,         // subu $24, $24, $28
-  0x03e07821,         // move $15, $31        # 32-bit move (addu)
+  0x03e07825,         // or $15, $31, zero
   0x0018c082,         // srl $24, $24, 2
   0x0320f809,         // jalr $25
   0x2718fffe          // subu $24, $24, 2
@@ -6177,7 +6177,7 @@ const uint32_t Mips_output_data_plt<size, big_endian>::plt0_entry_n32[] =
   0x8dd90000,         // lw $25, %lo(&GOTPLT[0])($14)
   0x25ce0000,         // addiu $14, $14, %lo(&GOTPLT[0])
   0x030ec023,         // subu $24, $24, $14
-  0x03e07821,         // move $15, $31        # 32-bit move (addu)
+  0x03e07825,         // or $15, $31, zero
   0x0018c082,         // srl $24, $24, 2
   0x0320f809,         // jalr $25
   0x2718fffe          // subu $24, $24, 2
@@ -6192,7 +6192,7 @@ const uint32_t Mips_output_data_plt<size, big_endian>::plt0_entry_n64[] =
   0xddd90000,         // ld $25, %lo(&GOTPLT[0])($14)
   0x25ce0000,         // addiu $14, $14, %lo(&GOTPLT[0])
   0x030ec023,         // subu $24, $24, $14
-  0x03e07821,         // move $15, $31        # 64-bit move (daddu)
+  0x03e07825,         // or $15, $31, zero
   0x0018c0c2,         // srl $24, $24, 3
   0x0320f809,         // jalr $25
   0x2718fffe          // subu $24, $24, 2
@@ -6229,7 +6229,7 @@ plt0_entry_micromips32_o32[] =
   0xff3c, 0x0000,      // lw $25, %lo(&GOTPLT[0])($28)
   0x339c, 0x0000,      // addiu $28, $28, %lo(&GOTPLT[0])
   0x0398, 0xc1d0,      // subu $24, $24, $28
-  0x001f, 0x7950,      // move $15, $31
+  0x001f, 0x7a90,      // or $15, $31, zero
   0x0318, 0x1040,      // srl $24, $24, 2
   0x03f9, 0x0f3c,      // jalr $25
   0x3318, 0xfffe       // subu $24, $24, 2
@@ -6631,7 +6631,7 @@ const uint32_t
 Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_normal_1[4] =
 {
   0x8f998010,         // lw t9,0x8010(gp)
-  0x03e07821,         // addu t7,ra,zero
+  0x03e07825,         // or t7,ra,zero
   0x0320f809,         // jalr t9,ra
   0x24180000          // addiu t8,zero,DYN_INDEX sign extended
 };
@@ -6643,7 +6643,7 @@ const uint32_t
 Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_normal_1_n64[4] =
 {
   0xdf998010,         // ld t9,0x8010(gp)
-  0x03e0782d,         // daddu t7,ra,zero
+  0x03e07825,         // or t7,ra,zero
   0x0320f809,         // jalr t9,ra
   0x64180000          // daddiu t8,zero,DYN_INDEX sign extended
 };
@@ -6655,7 +6655,7 @@ const uint32_t
 Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_normal_2[4] =
 {
   0x8f998010,         // lw t9,0x8010(gp)
-  0x03e07821,         // addu t7,ra,zero
+  0x03e07825,         // or t7,ra,zero
   0x0320f809,         // jalr t9,ra
   0x34180000          // ori t8,zero,DYN_INDEX unsigned
 };
@@ -6667,7 +6667,7 @@ const uint32_t
 Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_normal_2_n64[4] =
 {
   0xdf998010,         // ld t9,0x8010(gp)
-  0x03e0782d,         // daddu t7,ra,zero
+  0x03e07825,         // or t7,ra,zero
   0x0320f809,         // jalr t9,ra
   0x34180000          // ori t8,zero,DYN_INDEX unsigned
 };
@@ -6678,7 +6678,7 @@ template<int size, bool big_endian>
 const uint32_t Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_big[5] =
 {
   0x8f998010,         // lw t9,0x8010(gp)
-  0x03e07821,         // addu t7,ra,zero
+  0x03e07825,         // or t7,ra,zero
   0x3c180000,         // lui t8,DYN_INDEX
   0x0320f809,         // jalr t9,ra
   0x37180000          // ori t8,t8,DYN_INDEX
@@ -6691,7 +6691,7 @@ const uint32_t
 Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_big_n64[5] =
 {
   0xdf998010,         // ld t9,0x8010(gp)
-  0x03e0782d,         // daddu t7,ra,zero
+  0x03e07825,         // or t7,ra,zero
   0x3c180000,         // lui t8,DYN_INDEX
   0x0320f809,         // jalr t9,ra
   0x37180000          // ori t8,t8,DYN_INDEX
@@ -6788,7 +6788,7 @@ Mips_output_data_mips_stubs<size, big_endian>::
 lazy_stub_micromips32_normal_1[] =
 {
   0xff3c, 0x8010,     // lw t9,0x8010(gp)
-  0x001f, 0x7950,     // addu t7,ra,zero
+  0x001f, 0x7a90,     // or t7,ra,zero
   0x03f9, 0x0f3c,     // jalr ra,t9
   0x3300, 0x0000      // addiu t8,zero,DYN_INDEX sign extended
 };
@@ -6802,7 +6802,7 @@ Mips_output_data_mips_stubs<size, big_endian>::
 lazy_stub_micromips32_normal_1_n64[] =
 {
   0xdf3c, 0x8010,     // ld t9,0x8010(gp)
-  0x581f, 0x7950,     // daddu t7,ra,zero
+  0x001f, 0x7a90,     // or t7,ra,zero
   0x03f9, 0x0f3c,     // jalr ra,t9
   0x5f00, 0x0000      // daddiu t8,zero,DYN_INDEX sign extended
 };
@@ -6816,7 +6816,7 @@ Mips_output_data_mips_stubs<size, big_endian>::
 lazy_stub_micromips32_normal_2[] =
 {
   0xff3c, 0x8010,     // lw t9,0x8010(gp)
-  0x001f, 0x7950,     // addu t7,ra,zero
+  0x001f, 0x7a90,     // or t7,ra,zero
   0x03f9, 0x0f3c,     // jalr ra,t9
   0x5300, 0x0000      // ori t8,zero,DYN_INDEX unsigned
 };
@@ -6830,7 +6830,7 @@ Mips_output_data_mips_stubs<size, big_endian>::
 lazy_stub_micromips32_normal_2_n64[] =
 {
   0xdf3c, 0x8010,     // ld t9,0x8010(gp)
-  0x581f, 0x7950,     // daddu t7,ra,zero
+  0x001f, 0x7a90,     // or t7,ra,zero
   0x03f9, 0x0f3c,     // jalr ra,t9
   0x5300, 0x0000      // ori t8,zero,DYN_INDEX unsigned
 };
@@ -6842,7 +6842,7 @@ const uint32_t
 Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_micromips32_big[] =
 {
   0xff3c, 0x8010,     // lw t9,0x8010(gp)
-  0x001f, 0x7950,     // addu t7,ra,zero
+  0x001f, 0x7a90,     // or t7,ra,zero
   0x41b8, 0x0000,     // lui t8,DYN_INDEX
   0x03f9, 0x0f3c,     // jalr ra,t9
   0x5318, 0x0000      // ori t8,t8,DYN_INDEX
@@ -6855,7 +6855,7 @@ const uint32_t
 Mips_output_data_mips_stubs<size, big_endian>::lazy_stub_micromips32_big_n64[] =
 {
   0xdf3c, 0x8010,     // ld t9,0x8010(gp)
-  0x581f, 0x7950,     // daddu t7,ra,zero
+  0x001f, 0x7a90,     // or t7,ra,zero
   0x41b8, 0x0000,     // lui t8,DYN_INDEX
   0x03f9, 0x0f3c,     // jalr ra,t9
   0x5318, 0x0000      // ori t8,t8,DYN_INDEX
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index a2d7bb7..cecbfa6 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,34 @@
+2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test.
+	* ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-se.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto.
+	* ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto.
+	* ld-mips-elf/jalx-2.dd: Ditto.
+	* ld-mips-elf/mips16-pic-3.dd: Ditto.
+	* ld-mips-elf/pic-and-nonpic-3a.dd: Ditto.
+	* ld-mips-elf/pic-and-nonpic-3b.dd: Ditto.
+	* ld-mips-elf/pic-and-nonpic-5b.dd: Ditto.
+	* ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto.
+	* ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto.
+	* ld-mips-elf/stub-dynsym-1-10000.d: Ditto.
+	* ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto.
+	* ld-mips-elf/stub-dynsym-1-7fff.d: Ditto.
+	* ld-mips-elf/stub-dynsym-1-8000.d: Ditto.
+	* ld-mips-elf/stub-dynsym-1-fff0.d: Ditto.
+	* ld-mips-elf/tlsbin-o32.d: Ditto.
+	* ld-mips-elf/tlsdyn-o32-1.d: Ditto.
+	* ld-mips-elf/tlsdyn-o32-2.d: Ditto.
+	* ld-mips-elf/tlsdyn-o32-3.d: Ditto.
+	* ld-mips-elf/tlsdyn-o32.d: Ditto.
+	* ld-mips-elf/tlslib-o32.d: Ditto.
+
 2015-08-12  Jiong Wang  <jiong.wang@arm.com>
 
 	* ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul): Support all
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od
index c17dacb..95024db 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od
@@ -10,7 +10,7 @@ Disassembly of section \.plt:
 .*:	8dd90000 	lw	\$25,0\(\$14\)
 .*:	25ce0000 	addiu	\$14,\$14,0
 .*:	030ec023 	subu	\$24,\$24,\$14
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
@@ -188,17 +188,17 @@ Disassembly of section \.MIPS\.stubs:
 10101000 <_MIPS_STUBS_>:
 # Lazy-binding stub for f_iu.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	24180021 	li	\$24,33
 # Lazy-binding stub for f_ic.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	24180020 	li	\$24,32
 # Lazy-binding stub for f_iu_ic.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	2418001f 	li	\$24,31
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od
index fc0d4ea..cc7d355 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od
@@ -10,7 +10,7 @@ Disassembly of section \.plt:
 .*:	8dd90000 	lw	\$25,0\(\$14\)
 .*:	25ce0000 	addiu	\$14,\$14,0
 .*:	030ec023 	subu	\$24,\$24,\$14
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od
index c48ef7f..1e486ac 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od
@@ -12,7 +12,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od
index e76ca4f..0ce3634 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od
@@ -12,7 +12,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
@@ -70,7 +70,7 @@ Disassembly of section \.MIPS\.stubs:
 10101000 <_MIPS_STUBS_>:
 # Lazy-binding stub for f_ic.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	24180009 	li	\$24,9
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od
index 7fc547b..75a2f57 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od
@@ -12,7 +12,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od
index 712e651..0660bc8 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od
@@ -12,7 +12,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
@@ -286,17 +286,17 @@ Disassembly of section \.MIPS\.stubs:
 10101000 <_MIPS_STUBS_>:
 # Lazy-binding stub for f_iu.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	24180021 	li	\$24,33
 # Lazy-binding stub for f_ic.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	24180020 	li	\$24,32
 # Lazy-binding stub for f_iu_ic.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	2418001f 	li	\$24,31
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od
index 6e0d15a..1b17d46 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od
@@ -9,7 +9,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
@@ -55,7 +55,7 @@ Disassembly of section \.MIPS\.stubs:
 10101000 <_MIPS_STUBS_>:
 # Lazy-binding stub for f_iu.
 .*:	8f998010 	lw	\$25,-32752\(\$28\)
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0320f809 	jalr	\$25
 .*:	24180009 	li	\$24,9
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od
index 2d7b513..45a0df4 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od
@@ -11,7 +11,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od
index 4d0572b..ae884f0 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od
@@ -11,7 +11,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od
index 416509f..a18ecc5 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od
@@ -11,7 +11,7 @@ Disassembly of section \.plt:
 .*:	8f990000 	lw	\$25,0\(\$28\)
 .*:	279c0000 	addiu	\$28,\$28,0
 .*:	031cc023 	subu	\$24,\$24,\$28
-.*:	03e07821 	move	\$15,\$31
+.*:	03e07825 	move	\$15,\$31
 .*:	0018c082 	srl	\$24,\$24,0x2
 .*:	0320f809 	jalr	\$25
 .*:	2718fffe 	addiu	\$24,\$24,-2
diff --git a/ld/testsuite/ld-mips-elf/jalx-2.dd b/ld/testsuite/ld-mips-elf/jalx-2.dd
index 69985f6..3a7c1e1 100644
--- a/ld/testsuite/ld-mips-elf/jalx-2.dd
+++ b/ld/testsuite/ld-mips-elf/jalx-2.dd
@@ -5,8 +5,8 @@ Disassembly of section \.text:
 04400000 <external_function>:
  4400000:	27bdfff8 	addiu	sp,sp,-8
  4400004:	afbe0004 	sw	s8,4\(sp\)
- 4400008:	03a0f021 	move	s8,sp
- 440000c:	03c0e821 	move	sp,s8
+ 4400008:	03a0f025 	move	s8,sp
+ 440000c:	03c0e825 	move	sp,s8
  4400010:	8fbe0004 	lw	s8,4\(sp\)
  4400014:	27bd0008 	addiu	sp,sp,8
  4400018:	03e00008 	jr	ra
diff --git a/ld/testsuite/ld-mips-elf/mips16-pic-3.dd b/ld/testsuite/ld-mips-elf/mips16-pic-3.dd
index 93ba085..2c276ab 100644
--- a/ld/testsuite/ld-mips-elf/mips16-pic-3.dd
+++ b/ld/testsuite/ld-mips-elf/mips16-pic-3.dd
@@ -140,7 +140,7 @@ Disassembly of section \.text:
 .*:	44846000 	mtc1	a0,\$f12
 
 000404f0 <__call_fp_used2>:
-.*:	03e09021 	move	s2,ra
+.*:	03e09025 	move	s2,ra
 .*:	3c190004 	lui	t9,.*
 .*:	27390418 	addiu	t9,t9,.*
 .*:	0320f809 	jalr	t9
@@ -150,7 +150,7 @@ Disassembly of section \.text:
 .*:	00000000 	nop
 
 00040510 <__call_fp_used4>:
-.*:	03e09021 	move	s2,ra
+.*:	03e09025 	move	s2,ra
 .*:	3c190004 	lui	t9,.*
 .*:	27390428 	addiu	t9,t9,.*
 .*:	0320f809 	jalr	t9
@@ -160,7 +160,7 @@ Disassembly of section \.text:
 .*:	00000000 	nop
 
 00040530 <__call_fp_used8>:
-.*:	03e09021 	move	s2,ra
+.*:	03e09025 	move	s2,ra
 .*:	3c190004 	lui	t9,.*
 .*:	27390448 	addiu	t9,t9,.*
 .*:	0320f809 	jalr	t9
@@ -170,7 +170,7 @@ Disassembly of section \.text:
 .*:	00000000 	nop
 
 00040550 <__call_fp_extern2>:
-.*:	03e09021 	move	s2,ra
+.*:	03e09025 	move	s2,ra
 .*:	3c190004 	lui	t9,.*
 .*:	27390630 	addiu	t9,t9,.*
 .*:	0320f809 	jalr	t9
@@ -198,7 +198,7 @@ Disassembly of section \.text:
 .*:	44846000 	mtc1	a0,\$f12
 
 000405a0 <__call_fp_used6>:
-.*:	03e09021 	move	s2,ra
+.*:	03e09025 	move	s2,ra
 .*:	3c190004 	lui	t9,.*
 .*:	27390438 	addiu	t9,t9,.*
 .*:	0320f809 	jalr	t9
@@ -208,7 +208,7 @@ Disassembly of section \.text:
 .*:	00000000 	nop
 
 000405c0 <__call_fp_used10>:
-.*:	03e09021 	move	s2,ra
+.*:	03e09025 	move	s2,ra
 .*:	3c190004 	lui	t9,.*
 .*:	27390458 	addiu	t9,t9,.*
 .*:	0320f809 	jalr	t9
@@ -218,7 +218,7 @@ Disassembly of section \.text:
 .*:	00000000 	nop
 
 000405e0 <__call_fp_extern4>:
-.*:	03e09021 	move	s2,ra
+.*:	03e09025 	move	s2,ra
 .*:	3c190004 	lui	t9,.*
 .*:	27390640 	addiu	t9,t9,.*
 .*:	0320f809 	jalr	t9
@@ -234,7 +234,7 @@ Disassembly of section \.plt:
 .*:	8f990400 	lw	t9,1024\(gp\)
 .*:	279c0400 	addiu	gp,gp,1024
 .*:	031cc023 	subu	t8,t8,gp
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0018c082 	srl	t8,t8,0x2
 .*:	0320f809 	jalr	t9
 .*:	2718fffe 	addiu	t8,t8,-2
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.dd
index dfb4b27..3dcfe12 100644
--- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.dd
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.dd
@@ -33,7 +33,7 @@ Disassembly of section \.MIPS\.stubs:
 
 00000c00 <_MIPS_STUBS_>:
  c00:	8f998010 	lw	t9,-32752\(gp\)
- c04:	03e07821 	move	t7,ra
+ c04:	03e07825 	move	t7,ra
  c08:	0320f809 	jalr	t9
  c0c:	24180005 	li	t8,5
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd
index 151b4d2..9f7e078 100644
--- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd
@@ -14,7 +14,7 @@ Disassembly of section \.plt:
 .*:	8f991000 	lw	t9,4096\(gp\)
 .*:	279c1000 	addiu	gp,gp,4096
 .*:	031cc023 	subu	t8,t8,gp
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0018c082 	srl	t8,t8,0x2
 .*:	0320f809 	jalr	t9
 .*:	2718fffe 	addiu	t8,t8,-2
@@ -47,7 +47,7 @@ Disassembly of section \.MIPS\.stubs:
 
 00044030 <_MIPS_STUBS_>:
 .*:	8f998010 	lw	t9,-32752\(gp\)
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0320f809 	jalr	t9
 .*:	24180005 	li	t8,5
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd
index 9adfb31..23b2040 100644
--- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd
@@ -8,7 +8,7 @@ Disassembly of section \.plt:
 .*:	8f991000 	lw	t9,4096\(gp\)
 .*:	279c1000 	addiu	gp,gp,4096
 .*:	031cc023 	subu	t8,t8,gp
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0018c082 	srl	t8,t8,0x2
 .*:	0320f809 	jalr	t9
 .*:	2718fffe 	addiu	t8,t8,-2
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd
index 276d874..4242eac 100644
--- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd
@@ -19,7 +19,7 @@ Disassembly of section \.plt:
 .*:	8dd91000 	lw	t9,4096\(t2\)
 .*:	25ce1000 	addiu	t2,t2,4096
 .*:	030ec023 	subu	t8,t8,t2
-.*:	03e07821 	move	t3,ra
+.*:	03e07825 	move	t3,ra
 .*:	0018c082 	srl	t8,t8,0x2
 .*:	0320f809 	jalr	t9
 .*:	2718fffe 	addiu	t8,t8,-2
@@ -96,7 +96,7 @@ Disassembly of section \.MIPS\.stubs:
 
 000440a0 <_MIPS_STUBS_>:
    440a0:	8f998010 	lw	t9,-32752\(gp\)
-   440a4:	03e07821 	move	t3,ra
+   440a4:	03e07825 	move	t3,ra
    440a8:	0320f809 	jalr	t9
    440ac:	24180009 	li	t8,9
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd
index fbb3615..c98be4b 100644
--- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd
@@ -19,7 +19,7 @@ Disassembly of section \.plt:
 .*:	ddd91000 	ld	t9,4096\(t2\)
 .*:	25ce1000 	addiu	t2,t2,4096
 .*:	030ec023 	subu	t8,t8,t2
-.*:	03e0782d 	move	t3,ra
+.*:	03e07825 	move	t3,ra
 .*:	0018c0c2 	srl	t8,t8,0x3
 .*:	0320f809 	jalr	t9
 .*:	2718fffe 	addiu	t8,t8,-2
@@ -96,7 +96,7 @@ Disassembly of section \.MIPS\.stubs:
 
 0+440a0 <_MIPS_STUBS_>:
    440a0:	df998010 	ld	t9,-32752\(gp\)
-   440a4:	03e0782d 	move	t3,ra
+   440a4:	03e07825 	move	t3,ra
    440a8:	0320f809 	jalr	t9
    440ac:	64180009 	daddiu	t8,zero,9
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd
index e10a0af..e96e255 100644
--- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd
@@ -19,7 +19,7 @@ Disassembly of section \.plt:
 .*:	8f991000 	lw	t9,4096\(gp\)
 .*:	279c1000 	addiu	gp,gp,4096
 .*:	031cc023 	subu	t8,t8,gp
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0018c082 	srl	t8,t8,0x2
 .*:	0320f809 	jalr	t9
 .*:	2718fffe 	addiu	t8,t8,-2
@@ -96,7 +96,7 @@ Disassembly of section \.MIPS\.stubs:
 
 000440a0 <_MIPS_STUBS_>:
    440a0:	8f998010 	lw	t9,-32752\(gp\)
-   440a4:	03e07821 	move	t7,ra
+   440a4:	03e07825 	move	t7,ra
    440a8:	0320f809 	jalr	t9
    440ac:	24180009 	li	t8,9
 	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d
index e2d375b..df32fb1 100644
--- a/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d
+++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d
@@ -5,7 +5,7 @@ Disassembly of section \.MIPS\.stubs:
 
 .* <_MIPS_STUBS_>:
 .*:	8f998010 	lw	t9,-32752\(gp\)
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	3c180001 	lui	t8,0x1
 .*:	0320f809 	jalr	t9
 .*:	37180000 	ori	t8,t8,0x0
diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d
index d428f3d..8ff9686 100644
--- a/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d
+++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d
@@ -5,7 +5,7 @@ Disassembly of section \.MIPS\.stubs:
 
 .* <_MIPS_STUBS_>:
 .*:	8f998010 	lw	t9,-32752\(gp\)
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	3c180002 	lui	t8,0x2
 .*:	0320f809 	jalr	t9
 .*:	3718fe80 	ori	t8,t8,0xfe80
diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d
index e2b961f6..3ebb23d 100644
--- a/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d
+++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d
@@ -5,7 +5,7 @@ Disassembly of section \.MIPS\.stubs:
 
 .* <_MIPS_STUBS_>:
 .*:	8f998010 	lw	t9,-32752\(gp\)
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0320f809 	jalr	t9
 .*:	24187fff 	li	t8,32767
 .*:	00000000 	nop
diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d
index b1b1980..294d60a 100644
--- a/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d
+++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d
@@ -5,7 +5,7 @@ Disassembly of section \.MIPS\.stubs:
 
 .* <_MIPS_STUBS_>:
 .*:	8f998010 	lw	t9,-32752\(gp\)
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0320f809 	jalr	t9
 .*:	34188000 	li	t8,0x8000
 .*:	00000000 	nop
diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d b/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d
index 99ca9b2..7646c4d 100644
--- a/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d
+++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d
@@ -5,7 +5,7 @@ Disassembly of section \.MIPS\.stubs:
 
 .* <_MIPS_STUBS_>:
 .*:	8f998010 	lw	t9,-32752\(gp\)
-.*:	03e07821 	move	t7,ra
+.*:	03e07825 	move	t7,ra
 .*:	0320f809 	jalr	t9
 .*:	3418fff0 	li	t8,0xfff0
 .*:	00000000 	nop
diff --git a/ld/testsuite/ld-mips-elf/tlsbin-o32.d b/ld/testsuite/ld-mips-elf/tlsbin-o32.d
index dbf3ef3..769a890 100644
--- a/ld/testsuite/ld-mips-elf/tlsbin-o32.d
+++ b/ld/testsuite/ld-mips-elf/tlsbin-o32.d
@@ -8,7 +8,7 @@ Disassembly of section .text:
   4000d8:	0399e021 	addu	gp,gp,t9
   4000dc:	27bdfff0 	addiu	sp,sp,-16
   4000e0:	afbe0008 	sw	s8,8\(sp\)
-  4000e4:	03a0f021 	move	s8,sp
+  4000e4:	03a0f025 	move	s8,sp
   4000e8:	afbc0000 	sw	gp,0\(sp\)
   4000ec:	8f998018 	lw	t9,-32744\(gp\)
   4000f0:	27848020 	addiu	a0,gp,-32736
@@ -21,7 +21,7 @@ Disassembly of section .text:
   40010c:	0320f809 	jalr	t9
   400110:	00000000 	nop
   400114:	8fdc0000 	lw	gp,0\(s8\)
-  400118:	00401021 	move	v0,v0
+  400118:	00401025 	move	v0,v0
   40011c:	3c030000 	lui	v1,0x0
   400120:	24638000 	addiu	v1,v1,-32768
   400124:	00621821 	addu	v1,v1,v0
@@ -33,7 +33,7 @@ Disassembly of section .text:
   40013c:	3c030000 	lui	v1,0x0
   400140:	24639004 	addiu	v1,v1,-28668
   400144:	00621821 	addu	v1,v1,v0
-  400148:	03c0e821 	move	sp,s8
+  400148:	03c0e825 	move	sp,s8
   40014c:	8fbe0008 	lw	s8,8\(sp\)
   400150:	03e00008 	jr	ra
   400154:	27bd0010 	addiu	sp,sp,16
diff --git a/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d b/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d
index 6b8f96c..011df6c 100644
--- a/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d
+++ b/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
   .*:	0399e021 	addu	gp,gp,t9
   .*:	27bdfff0 	addiu	sp,sp,-16
   .*:	afbe0008 	sw	s8,8\(sp\)
-  .*:	03a0f021 	move	s8,sp
+  .*:	03a0f025 	move	s8,sp
   .*:	afbc0000 	sw	gp,0\(sp\)
   .*:	8f998018 	lw	t9,-32744\(gp\)
   .*:	27848028 	addiu	a0,gp,-32728
@@ -28,7 +28,7 @@ Disassembly of section .text:
   .*:	0320f809 	jalr	t9
   .*:	00000000 	nop
   .*:	8fdc0000 	lw	gp,0\(s8\)
-  .*:	00401021 	move	v0,v0
+  .*:	00401025 	move	v0,v0
   .*:	3c030000 	lui	v1,0x0
   .*:	24638000 	addiu	v1,v1,-32768
   .*:	00621821 	addu	v1,v1,v0
@@ -43,7 +43,7 @@ Disassembly of section .text:
   .*:	3c030000 	lui	v1,0x0
   .*:	24639004 	addiu	v1,v1,-28668
   .*:	00621821 	addu	v1,v1,v0
-  .*:	03c0e821 	move	sp,s8
+  .*:	03c0e825 	move	sp,s8
   .*:	8fbe0008 	lw	s8,8\(sp\)
   .*:	03e00008 	jr	ra
   .*:	27bd0010 	addiu	sp,sp,16
@@ -59,7 +59,7 @@ Disassembly of section .text:
   .*:	0399e021 	addu	gp,gp,t9
   .*:	27bdfff0 	addiu	sp,sp,-16
   .*:	afbe0008 	sw	s8,8\(sp\)
-  .*:	03a0f021 	move	s8,sp
+  .*:	03a0f025 	move	s8,sp
   .*:	afbc0000 	sw	gp,0\(sp\)
   .*:	8f998018 	lw	t9,-32744\(gp\)
   .*:	27848028 	addiu	a0,gp,-32728
@@ -78,7 +78,7 @@ Disassembly of section .text:
   .*:	0320f809 	jalr	t9
   .*:	00000000 	nop
   .*:	8fdc0000 	lw	gp,0\(s8\)
-  .*:	00401021 	move	v0,v0
+  .*:	00401025 	move	v0,v0
   .*:	3c030000 	lui	v1,0x0
   .*:	24638000 	addiu	v1,v1,-32768
   .*:	00621821 	addu	v1,v1,v0
@@ -93,7 +93,7 @@ Disassembly of section .text:
   .*:	3c030000 	lui	v1,0x0
   .*:	24639004 	addiu	v1,v1,-28668
   .*:	00621821 	addu	v1,v1,v0
-  .*:	03c0e821 	move	sp,s8
+  .*:	03c0e825 	move	sp,s8
   .*:	8fbe0008 	lw	s8,8\(sp\)
   .*:	03e00008 	jr	ra
   .*:	27bd0010 	addiu	sp,sp,16
diff --git a/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d b/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d
index 6b8f96c..011df6c 100644
--- a/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d
+++ b/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
   .*:	0399e021 	addu	gp,gp,t9
   .*:	27bdfff0 	addiu	sp,sp,-16
   .*:	afbe0008 	sw	s8,8\(sp\)
-  .*:	03a0f021 	move	s8,sp
+  .*:	03a0f025 	move	s8,sp
   .*:	afbc0000 	sw	gp,0\(sp\)
   .*:	8f998018 	lw	t9,-32744\(gp\)
   .*:	27848028 	addiu	a0,gp,-32728
@@ -28,7 +28,7 @@ Disassembly of section .text:
   .*:	0320f809 	jalr	t9
   .*:	00000000 	nop
   .*:	8fdc0000 	lw	gp,0\(s8\)
-  .*:	00401021 	move	v0,v0
+  .*:	00401025 	move	v0,v0
   .*:	3c030000 	lui	v1,0x0
   .*:	24638000 	addiu	v1,v1,-32768
   .*:	00621821 	addu	v1,v1,v0
@@ -43,7 +43,7 @@ Disassembly of section .text:
   .*:	3c030000 	lui	v1,0x0
   .*:	24639004 	addiu	v1,v1,-28668
   .*:	00621821 	addu	v1,v1,v0
-  .*:	03c0e821 	move	sp,s8
+  .*:	03c0e825 	move	sp,s8
   .*:	8fbe0008 	lw	s8,8\(sp\)
   .*:	03e00008 	jr	ra
   .*:	27bd0010 	addiu	sp,sp,16
@@ -59,7 +59,7 @@ Disassembly of section .text:
   .*:	0399e021 	addu	gp,gp,t9
   .*:	27bdfff0 	addiu	sp,sp,-16
   .*:	afbe0008 	sw	s8,8\(sp\)
-  .*:	03a0f021 	move	s8,sp
+  .*:	03a0f025 	move	s8,sp
   .*:	afbc0000 	sw	gp,0\(sp\)
   .*:	8f998018 	lw	t9,-32744\(gp\)
   .*:	27848028 	addiu	a0,gp,-32728
@@ -78,7 +78,7 @@ Disassembly of section .text:
   .*:	0320f809 	jalr	t9
   .*:	00000000 	nop
   .*:	8fdc0000 	lw	gp,0\(s8\)
-  .*:	00401021 	move	v0,v0
+  .*:	00401025 	move	v0,v0
   .*:	3c030000 	lui	v1,0x0
   .*:	24638000 	addiu	v1,v1,-32768
   .*:	00621821 	addu	v1,v1,v0
@@ -93,7 +93,7 @@ Disassembly of section .text:
   .*:	3c030000 	lui	v1,0x0
   .*:	24639004 	addiu	v1,v1,-28668
   .*:	00621821 	addu	v1,v1,v0
-  .*:	03c0e821 	move	sp,s8
+  .*:	03c0e825 	move	sp,s8
   .*:	8fbe0008 	lw	s8,8\(sp\)
   .*:	03e00008 	jr	ra
   .*:	27bd0010 	addiu	sp,sp,16
diff --git a/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d b/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d
index 758a4f2..3828aca 100644
--- a/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d
+++ b/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
   .*:	0399e021 	addu	gp,gp,t9
   .*:	27bdfff0 	addiu	sp,sp,-16
   .*:	afbe0008 	sw	s8,8\(sp\)
-  .*:	03a0f021 	move	s8,sp
+  .*:	03a0f025 	move	s8,sp
   .*:	afbc0000 	sw	gp,0\(sp\)
   .*:	8f998018 	lw	t9,-32744\(gp\)
   .*:	27848028 	addiu	a0,gp,-32728
@@ -28,7 +28,7 @@ Disassembly of section .text:
   .*:	0320f809 	jalr	t9
   .*:	00000000 	nop
   .*:	8fdc0000 	lw	gp,0\(s8\)
-  .*:	00401021 	move	v0,v0
+  .*:	00401025 	move	v0,v0
   .*:	3c030000 	lui	v1,0x0
   .*:	24638000 	addiu	v1,v1,-32768
   .*:	00621821 	addu	v1,v1,v0
@@ -43,7 +43,7 @@ Disassembly of section .text:
   .*:	3c030000 	lui	v1,0x0
   .*:	24639004 	addiu	v1,v1,-28668
   .*:	00621821 	addu	v1,v1,v0
-  .*:	03c0e821 	move	sp,s8
+  .*:	03c0e825 	move	sp,s8
   .*:	8fbe0008 	lw	s8,8\(sp\)
   .*:	03e00008 	jr	ra
   .*:	27bd0010 	addiu	sp,sp,16
@@ -55,7 +55,7 @@ Disassembly of section .text:
   .*:	0399e021 	addu	gp,gp,t9
   .*:	27bdfff0 	addiu	sp,sp,-16
   .*:	afbe0008 	sw	s8,8\(sp\)
-  .*:	03a0f021 	move	s8,sp
+  .*:	03a0f025 	move	s8,sp
   .*:	afbc0000 	sw	gp,0\(sp\)
   .*:	8f998018 	lw	t9,-32744\(gp\)
   .*:	27848028 	addiu	a0,gp,-32728
@@ -74,7 +74,7 @@ Disassembly of section .text:
   .*:	0320f809 	jalr	t9
   .*:	00000000 	nop
   .*:	8fdc0000 	lw	gp,0\(s8\)
-  .*:	00401021 	move	v0,v0
+  .*:	00401025 	move	v0,v0
   .*:	3c030000 	lui	v1,0x0
   .*:	24638000 	addiu	v1,v1,-32768
   .*:	00621821 	addu	v1,v1,v0
@@ -89,7 +89,7 @@ Disassembly of section .text:
   .*:	3c030000 	lui	v1,0x0
   .*:	24639004 	addiu	v1,v1,-28668
   .*:	00621821 	addu	v1,v1,v0
-  .*:	03c0e821 	move	sp,s8
+  .*:	03c0e825 	move	sp,s8
   .*:	8fbe0008 	lw	s8,8\(sp\)
   .*:	03e00008 	jr	ra
   .*:	27bd0010 	addiu	sp,sp,16
diff --git a/ld/testsuite/ld-mips-elf/tlsdyn-o32.d b/ld/testsuite/ld-mips-elf/tlsdyn-o32.d
index ea50960..e3f9ccb 100644
--- a/ld/testsuite/ld-mips-elf/tlsdyn-o32.d
+++ b/ld/testsuite/ld-mips-elf/tlsdyn-o32.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
   .*:	0399e021 	addu	gp,gp,t9
   .*:	27bdfff0 	addiu	sp,sp,-16
   .*:	afbe0008 	sw	s8,8\(sp\)
-  .*:	03a0f021 	move	s8,sp
+  .*:	03a0f025 	move	s8,sp
   .*:	afbc0000 	sw	gp,0\(sp\)
   .*:	8f998018 	lw	t9,-32744\(gp\)
   .*:	27848034 	addiu	a0,gp,-32716
@@ -28,7 +28,7 @@ Disassembly of section .text:
   .*:	0320f809 	jalr	t9
   .*:	00000000 	nop
   .*:	8fdc0000 	lw	gp,0\(s8\)
-  .*:	00401021 	move	v0,v0
+  .*:	00401025 	move	v0,v0
   .*:	3c030000 	lui	v1,0x0
   .*:	24638000 	addiu	v1,v1,-32768
   .*:	00621821 	addu	v1,v1,v0
@@ -43,7 +43,7 @@ Disassembly of section .text:
   .*:	3c030000 	lui	v1,0x0
   .*:	24639004 	addiu	v1,v1,-28668
   .*:	00621821 	addu	v1,v1,v0
-  .*:	03c0e821 	move	sp,s8
+  .*:	03c0e825 	move	sp,s8
   .*:	8fbe0008 	lw	s8,8\(sp\)
   .*:	03e00008 	jr	ra
   .*:	27bd0010 	addiu	sp,sp,16
diff --git a/ld/testsuite/ld-mips-elf/tlslib-o32.d b/ld/testsuite/ld-mips-elf/tlslib-o32.d
index 066f284..9ac943b 100644
--- a/ld/testsuite/ld-mips-elf/tlslib-o32.d
+++ b/ld/testsuite/ld-mips-elf/tlslib-o32.d
@@ -9,7 +9,7 @@ Disassembly of section .text:
  .*:	0399e021 	addu	gp,gp,t9
  .*:	27bdfff0 	addiu	sp,sp,-16
  .*:	afbe0008 	sw	s8,8\(sp\)
- .*:	03a0f021 	move	s8,sp
+ .*:	03a0f025 	move	s8,sp
  .*:	afbc0000 	sw	gp,0\(sp\)
  .*:	8f998018 	lw	t9,-32744\(gp\)
  .*:	27848020 	addiu	a0,gp,-32736
@@ -22,7 +22,7 @@ Disassembly of section .text:
  .*:	0320f809 	jalr	t9
  .*:	00000000 	nop
  .*:	8fdc0000 	lw	gp,0\(s8\)
- .*:	00401021 	move	v0,v0
+ .*:	00401025 	move	v0,v0
  .*:	3c030000 	lui	v1,0x0
  .*:	24638000 	addiu	v1,v1,-32768
  .*:	00621821 	addu	v1,v1,v0
@@ -30,7 +30,7 @@ Disassembly of section .text:
  .*:	8f83801c 	lw	v1,-32740\(gp\)
  .*:	00000000 	nop
  .*:	00621821 	addu	v1,v1,v0
- .*:	03c0e821 	move	sp,s8
+ .*:	03c0e825 	move	sp,s8
  .*:	8fbe0008 	lw	s8,8\(sp\)
  .*:	03e00008 	jr	ra
  .*:	27bd0010 	addiu	sp,sp,16
@@ -40,7 +40,7 @@ Disassembly of section .MIPS.stubs:
 
 .* <_MIPS_STUBS_>:
  .*:	8f998010 	lw	t9,-32752\(gp\)
- .*:	03e07821 	move	t7,ra
+ .*:	03e07825 	move	t7,ra
  .*:	0320f809 	jalr	t9
  .*:	241800.* 	li	t8,.*
 	...
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9367d1c..ac0b433 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* micromips-opc.c (micromips_opcodes): Re-order table so that move
+	based on 'or' is first.
+	* mips-opc.c (mips_builtin_opcodes): Ditto.
+
 2015-08-11  Nick Clifton  <nickc@redhat.com>
 
 	PR 18800
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 66c5418..92ae40c 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -299,16 +299,15 @@ const struct mips_opcode micromips_opcodes[] =
 {"li",			"t,I",		0,    (int) M_LI,	INSN_MACRO,		0,		I1,		0,	0 },
 {"move",		"d,s",		0,    (int) M_MOVE,	INSN_MACRO,		0,		I1,		0,	0 },
 {"move",		"mp,mj",	    0x0c00,     0xfc00,	WR_1|RD_2,		0,		I1,		0,	0 },
+{"move",		"d,s",		0x00000290, 0xffe007ff,	WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 }, /* or */
 {"move",		"d,s",		0x58000150, 0xffe007ff,	WR_1|RD_2,		INSN2_ALIAS,	I3,		0,	0 }, /* daddu */
 {"move",		"d,s",		0x00000150, 0xffe007ff,	WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 }, /* addu */
-{"move",		"d,s",		0x00000290, 0xffe007ff,	WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 }, /* or */
 {"b",			"mD",		    0xcc00,     0xfc00,	UBD,			0,		I1,		0,	0 },
 {"b",			"p",		0x94000000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 }, /* beq 0, 0 */
 {"b",			"p",		0x40400000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 }, /* bgez 0 */
 {"bal",			"p",		0x40600000, 0xffff0000,	WR_31|UBD,		INSN2_ALIAS|BD32, I1,		0,	0 }, /* bgezal 0 */
 {"bals",		"p",		0x42600000, 0xffff0000,	WR_31|UBD,		INSN2_ALIAS|BD16, I1,		0,	0 }, /* bgezals 0 */
 {"bc",			"p",		0x40e00000, 0xffff0000,	NODS,			INSN2_ALIAS|UBR,  I1,		0,	0 }, /* beqzc 0 */
-
 {"abs",			"d,v",		0,    (int) M_ABS,	INSN_MACRO,		0,		I1,		0,	0 },
 {"abs.d",		"T,V",		0x5400237b, 0xfc00ffff,	WR_1|RD_2|FP_D,		0,		I1,		0,	0 },
 {"abs.s",		"T,V",		0x5400037b, 0xfc00ffff,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index efe6cf2..b29a8ed 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -425,9 +425,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"li",			"t,i",		0x34000000, 0xffe00000, WR_1,			INSN2_ALIAS,	I1,		0,	0 }, /* ori */
 {"li",			"t,I",		0,    (int) M_LI,	INSN_MACRO,		0,		I1,		0,	0 },
 {"move",		"d,s",		0,    (int) M_MOVE,	INSN_MACRO,		0,		I1,		0,	0 },
+{"move",		"d,s",		0x00000025, 0xfc1f07ff,	WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 },/* or */
 {"move",		"d,s",		0x0000002d, 0xfc1f07ff, WR_1|RD_2,		INSN2_ALIAS,	I3,		0,	0 },/* daddu */
 {"move",		"d,s",		0x00000021, 0xfc1f07ff, WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 },/* addu */
-{"move",		"d,s",		0x00000025, 0xfc1f07ff,	WR_1|RD_2,		INSN2_ALIAS,	I1,		0,	0 },/* or */
 {"b",			"p",		0x10000000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 },/* beq 0,0 */
 {"b",			"p",		0x04010000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1,		0,	0 },/* bgez 0 */
 {"nal",			"",		0x04100000, 0xffffffff,	WR_31|CBD,		INSN2_ALIAS,	I1,		0,	0 },/* bltzal 0 */
author	Simon Dardis <simon.dardis@imgtec.com>	2015-08-12 17:06:35 +0100
committer	Robert Suchanek <robert.suchanek@imgtec.com>	2015-08-12 17:10:22 +0100
commit	40fc1451c63d21a1448bb21e39a7b70ecb959213 (patch)
tree	a614e0a966ad575b5315d7dd97f633dd1adf30e3
parent	b6dafabfb18e3ab207a1818ebe68e30337b5515d (diff)
download	gdb-40fc1451c63d21a1448bb21e39a7b70ecb959213.zip gdb-40fc1451c63d21a1448bb21e39a7b70ecb959213.tar.gz gdb-40fc1451c63d21a1448bb21e39a7b70ecb959213.tar.bz2