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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:19 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:19 +0100 |
| commit | 0a57e14ffa4c2900f64780375282dc5dc493e250 (patch) | |
| tree | b9c6c7bf07d52059c1d44eacaacb461caf7df28b | |
| parent | c469c86473273e115b267a6f8c93c8942deb93c4 (diff) | |
| download | gdb-0a57e14ffa4c2900f64780375282dc5dc493e250.zip gdb-0a57e14ffa4c2900f64780375282dc5dc493e250.tar.gz gdb-0a57e14ffa4c2900f64780375282dc5dc493e250.tar.bz2 | |
[binutils][aarch64] New sve_size_sd2 iclass.
Define new sve_size_sd2 iclass to distinguish between the two variants
of ldnt1sb and ldnt1sh.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_sd2 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_sd2 iclass decode.
* aarch64-opc.c (fields): Handle SVE_sz2 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 1 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.h | 1 |
7 files changed, 24 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index ca6ffd1..3d17921 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,9 @@ 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass. + +2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ac440bc..8749993 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -594,6 +594,7 @@ enum aarch64_insn_class sve_size_hsd, sve_size_hsd2, sve_size_sd, + sve_size_sd2, testbranch, cryptosm3, cryptosm4, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 279b4c8..f139282 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,14 @@ 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_sd2 iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_sd2 iclass decode. + * aarch64-opc.c (fields): Handle SVE_sz2 field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. + +2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index d4f498f..6627b54 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1659,6 +1659,10 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0); break; + case sve_size_sd2: + insert_field (FLD_SVE_sz2, &inst->value, aarch64_get_variant (inst), 0); + break; + case sve_size_hsd2: insert_field (FLD_SVE_size, &inst->value, aarch64_get_variant (inst) + 1, 0); diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 844c6ab..35576b3 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2810,6 +2810,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = extract_field (FLD_SVE_sz, inst->value, 0); break; + case sve_size_sd2: + variant = extract_field (FLD_SVE_sz2, inst->value, 0); + break; + case sve_size_hsd2: i = extract_field (FLD_SVE_size, inst->value, 0); if (i < 1) diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 23b1503..1f85294 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -314,6 +314,7 @@ const aarch64_field fields[] = { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */ { 22, 1 }, /* SVE_sz: 1-bit element size select. */ { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */ + { 30, 1 }, /* SVE_sz2: 1-bit element size select. */ { 16, 4 }, /* SVE_tsz: triangular size select. */ { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */ { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 8803bca..8d18175 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -141,6 +141,7 @@ enum aarch64_field_kind FLD_SVE_rot3, FLD_SVE_sz, FLD_SVE_size, + FLD_SVE_sz2, FLD_SVE_tsz, FLD_SVE_tszh, FLD_SVE_tszl_8, |