[ gas/ChangeLog ]

	* config/tc-mips.c (macro_build): Test for currently active
	mips16 option.
	(mips16_ip): Reject invalid opcodes.

	[ opcodes/ChangeLog ]
	* mips16-opc.c (I1, I32, I64): New shortcut defines.
	(mips16_opcodes): Change membership of instructions to their
	lowest baseline ISA.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips.exp: Run new tests.
	* gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s,
	gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.

11 files changed, 332 insertions, 135 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d8ea270..39dfcc4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build): Test for currently active
+	mips16 option.
+	(mips16_ip): Reject invalid opcodes.
+
 2006-05-11  Carlos O'Donell  <carlos@codesourcery.com>
 
 	* doc/as.texinfo: Rename "Index" to "AS Index",
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 3108d0a..75c3ae9 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -3015,7 +3015,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	 || mo->pinfo == INSN_MACRO
 	 || !OPCODE_IS_MEMBER (mo,
 			       (mips_opts.isa
-				| (file_ase_mips16 ? INSN_MIPS16 : 0)
+				| (mips_opts.mips16 ? INSN_MIPS16 : 0)
 				| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
 			       mips_opts.arch)
 	 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
@@ -8032,6 +8032,9 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 
       if (OPCODE_IS_MEMBER (insn,
 			    (mips_opts.isa
+			     /* We don't check for mips_opts.mips16 here since
+			        we want to allow jalx if -mips16 was specified
+			        on the command line.  */
 			     | (file_ase_mips16 ? INSN_MIPS16 : 0)
 	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
 	      		     | (mips_opts.ase_dsp ? INSN_DSP : 0)
@@ -9467,8 +9470,38 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
   argsstart = s;
   for (;;)
     {
+      bfd_boolean ok;
+
       assert (strcmp (insn->name, str) == 0);
 
+      if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
+	ok = TRUE;
+      else
+	ok = FALSE;
+
+      if (! ok)
+	{
+	  if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
+	      && strcmp (insn->name, insn[1].name) == 0)
+	    {
+	      ++insn;
+	      continue;
+	    }
+	  else
+	    {
+	      if (!insn_error)
+		{
+		  static char buf[100];
+		  sprintf (buf,
+			   _("opcode not supported on this processor: %s (%s)"),
+			   mips_cpu_info_from_arch (mips_opts.arch)->name,
+			   mips_cpu_info_from_isa (mips_opts.isa)->name);
+		  insn_error = buf;
+		}
+	      return;
+	    }
+	}
+
       create_insn (ip, insn);
       imm_expr.X_op = O_absent;
       imm_reloc[0] = BFD_RELOC_UNUSED;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e9745b1..2332821 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/mips.exp: Run new tests.
+	* gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s,
+	gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
+
 2006-05-11  Paul Brook  <paul@codesourcery.com>
 
 	* gas/arm/local_function.d: New test.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index a65a4c5..e275107 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -777,8 +777,12 @@ if { [istarget mips*-*-vxworks*] } {
 	}
     }
     if { !$no_mips16 } { 
+        # Check MIPS16e extensions
+        run_dump_test_arches "mips16e" 	[mips_arch_list_matching mips32]
         run_dump_test "mips16e-jrc"
         run_dump_test "mips16e-save"
+        run_dump_test "mips16e-64"
+        run_list_test "mips16e-64" "-march=mips32"
     }
     run_dump_test "vxworks1"
     run_dump_test "vxworks1-xgot"
diff --git a/gas/testsuite/gas/mips/mips16e-64.d b/gas/testsuite/gas/mips/mips16e-64.d
new file mode 100644
index 0000000..9eb098f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric -mmips:16
+#as: -march=mips64
+#name: MIPS16e-64
+#source: mips16e-64.s
+
+# Test the 64bit instructions of mips16e.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+0x00000000 ecd1      	sew	\$4
+0x00000002 ec51      	zew	\$4
+0x00000004 6500      	nop
+0x00000006 6500      	nop
+0x00000008 6500      	nop
+0x0000000a 6500      	nop
+0x0000000c 6500      	nop
+0x0000000e 6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16e-64.l b/gas/testsuite/gas/mips/mips16e-64.l
new file mode 100644
index 0000000..8df0c05
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: opcode not supported on this processor: .* (.*) `sew'
+.*: Error: opcode not supported on this processor: .* (.*) `zew'
diff --git a/gas/testsuite/gas/mips/mips16e-64.s b/gas/testsuite/gas/mips/mips16e-64.s
new file mode 100644
index 0000000..39b3597
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.s
@@ -0,0 +1,9 @@
+# Test the 64bit instructions of mips16e.
+
+	.text
+	.set	mips16
+
+	sew	$4
+	zew	$4
+
+	.p2align 4
diff --git a/gas/testsuite/gas/mips/mips16e.d b/gas/testsuite/gas/mips/mips16e.d
new file mode 100644
index 0000000..53aa0d3
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e.d
@@ -0,0 +1,50 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS16e
+#as: -32
+
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> eac0      	jalrc	\$2
+0+0002 <[^>]*> eac0      	jalrc	\$2
+0+0004 <[^>]*> e8a0      	jrc	\$31
+0+0006 <[^>]*> ea80      	jrc	\$2
+0+0008 <[^>]*> eac0      	jalrc	\$2
+0+000a <[^>]*> eac0      	jalrc	\$2
+0+000c <[^>]*> eac0      	jalrc	\$2
+0+000e <[^>]*> eac0      	jalrc	\$2
+0+0010 <[^>]*> e8a0      	jrc	\$31
+0+0012 <[^>]*> ea80      	jrc	\$2
+0+0014 <[^>]*> e8a0      	jrc	\$31
+0+0016 <[^>]*> ea80      	jrc	\$2
+0+0018 <[^>]*> eac0      	jalrc	\$2
+0+001a <[^>]*> 1800 0000 	jal	00000000 <[^>]*>
+			1a: R_MIPS16_26	foo
+0+001e <[^>]*> 4281      	addiu	\$4,\$2,1
+0+0020 <[^>]*> eac0      	jalrc	\$2
+0+0022 <[^>]*> 1800 0000 	jal	00000000 <[^>]*>
+			22: R_MIPS16_26	foo
+0+0026 <[^>]*> 6500      	nop
+0+0028 <[^>]*> 6782      	move	\$4,\$2
+0+002a <[^>]*> eac0      	jalrc	\$2
+0+002c <[^>]*> 6782      	move	\$4,\$2
+0+002e <[^>]*> ea80      	jrc	\$2
+0+0030 <[^>]*> 6782      	move	\$4,\$2
+0+0032 <[^>]*> e8a0      	jrc	\$31
+0+0034 <[^>]*> ec91      	seb	\$4
+0+0036 <[^>]*> ecb1      	seh	\$4
+0+0038 <[^>]*> ec11      	zeb	\$4
+0+003a <[^>]*> ec31      	zeh	\$4
+0+003c <[^>]*> 64c1      	save	8,\$31
+0+003e <[^>]*> 64c0      	save	128,\$31
+0+0040 <[^>]*> 64e2      	save	16,\$31,\$16
+0+0042 <[^>]*> 64f2      	save	16,\$31,\$16-\$17
+0+0044 <[^>]*> 64df      	save	120,\$31,\$17
+0+0046 <[^>]*> f010 64e1 	save	136,\$31,\$16
+0+004a <[^>]*> f004 64f2 	save	\$4,16,\$31,\$16-\$17
+0+004e <[^>]*> f308 64e2 	save	\$4-\$5,16,\$31,\$16,\$18-\$20
+0+0052 <[^>]*> f30c 64f2 	save	\$4-\$6,16,\$31,\$16-\$20
+0+0056 <[^>]*> f70e 64d2 	save	\$4-\$7,16,\$31,\$17-\$30
+0+005a <[^>]*> f30a 64e2 	save	\$4-\$5,16,\$31,\$16,\$18-\$20,\$6-\$7
+0+005e <[^>]*> 6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16e.s b/gas/testsuite/gas/mips/mips16e.s
new file mode 100644
index 0000000..72e2d09
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e.s
@@ -0,0 +1,58 @@
+# Test the mips16e instruction set.
+
+	.set	mips16
+	.text
+stuff:
+	# explicit compact jumps
+	jalrc	$2
+	jalrc	$31,$2
+	jrc	$31
+	jrc	$2
+	
+	# these jumps should all be converted to compact versions
+	jalr	$2
+	jalr	$31,$2
+	jal	$2
+	jal	$31,$2
+	jr	$31
+	jr	$2
+	j	$31
+	j	$2
+	
+	# make sure unconditional jumps don't swap with compact jumps
+	# and vice versa.
+	jalr	$2
+	.set	noreorder
+	jal	foo		# mustn't swap with previous jalr
+	addu	$4,$2,1
+	.set	reorder
+	jalr	$2
+	jal	foo
+	
+	move	$4,$2
+1:	jal	$2		# can't swap with move
+		
+	move	$4,$2
+1:	jr	$2		# can't swap with move
+	
+	move	$4,$2
+1:	jr	$31		# can't swap with move
+	
+	seb	$4
+	seh	$4
+	zeb	$4
+	zeh	$4
+
+	save	$31,8
+	save	$31,128
+	save	$31,$16,16
+	save	$31,$16-$17,16
+	save	$31,$17,120
+	save	$31,$16,136
+	save	$4,$31,$16-$17,16
+	save	$4-$5,$31,$16,$18,$19,$20,16
+	save	$4-$6,$31,$16-$20,16
+	save	$4-$7,$31,$17,$18-$30,16
+	save	$4-$5,$31,$16,$18,$19,$20,16,$6-$7
+	
+	.p2align 4
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b3c5b6f..37d1931 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+
+	* mips16-opc.c (I1, I32, I64): New shortcut defines.
+	(mips16_opcodes): Change membership of instructions to their
+	lowest baseline ISA.
+
 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (grps): Update sgdt/sidt for 64bit.
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 24b6107..8144986 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -58,59 +58,61 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
 
 #define TRAP	INSN_TRAP
 
+#define I1	INSN_ISA1
 #define I3	INSN_ISA3
-
-#define T3      INSN_3900
+#define I32	INSN_ISA32
+#define I64	INSN_ISA64
+#define T3	INSN_3900
 
 const struct mips_opcode mips16_opcodes[] =
 {
 /* name,    args,	match,	mask,	pinfo,         	pinfo2, membership */
-{"nop",	    "",		0x6500, 0xffff, RD_Z,		0,	0 }, /* move $0,$Z */
-{"la",	    "x,A",	0x0800, 0xf800, WR_x|RD_PC,	0,	0 },
-{"abs",	    "x,w",	0, (int) M_ABS, INSN_MACRO,	0,	0 },
-{"addiu",   "y,x,4",	0x4000, 0xf810, WR_y|RD_x,	0,	0 },
-{"addiu",   "x,k",	0x4800, 0xf800, WR_x|RD_x,	0,	0 },
-{"addiu",   "S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	0 },
-{"addiu",   "S,S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	0 },
-{"addiu",   "x,P,V",	0x0800, 0xf800, WR_x|RD_PC,	0,	0 },
-{"addiu",   "x,S,V",	0x0000, 0xf800, WR_x|RD_SP,	0,	0 },
-{"addu",    "z,v,y",	0xe001, 0xf803, WR_z|RD_x|RD_y,	0,	0 },
-{"addu",    "y,x,4",	0x4000, 0xf810, WR_y|RD_x,	0,	0 },
-{"addu",    "x,k",	0x4800, 0xf800, WR_x|RD_x,	0,	0 },
-{"addu",    "S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	0 },
-{"addu",    "S,S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	0 },
-{"addu",    "x,P,V",	0x0800, 0xf800, WR_x|RD_PC,	0,	0 },
-{"addu",    "x,S,V",	0x0000, 0xf800, WR_x|RD_SP,	0,	0 },
-{"and",	    "x,y",	0xe80c, 0xf81f, WR_x|RD_x|RD_y,	0,	0 },
-{"b",	    "q",	0x1000, 0xf800, BR,		0,	0 },
-{"beq",	    "x,y,p",	0, (int) M_BEQ, INSN_MACRO,	0,	0 },
-{"beq",     "x,U,p",	0, (int) M_BEQ_I, INSN_MACRO,	0,	0 },
-{"beqz",    "x,p",	0x2000, 0xf800, BR|RD_x,	0,	0 },
-{"bge",	    "x,y,p",	0, (int) M_BGE, INSN_MACRO,	0,	0 },
-{"bge",     "x,8,p",	0, (int) M_BGE_I, INSN_MACRO,	0,	0 },
-{"bgeu",    "x,y,p",	0, (int) M_BGEU, INSN_MACRO,	0,	0 },
-{"bgeu",    "x,8,p",	0, (int) M_BGEU_I, INSN_MACRO,	0,	0 },
-{"bgt",	    "x,y,p",	0, (int) M_BGT, INSN_MACRO,	0,	0 },
-{"bgt",     "x,8,p",	0, (int) M_BGT_I, INSN_MACRO,	0,	0 },
-{"bgtu",    "x,y,p",	0, (int) M_BGTU, INSN_MACRO,	0,	0 },
-{"bgtu",    "x,8,p",	0, (int) M_BGTU_I, INSN_MACRO,	0,	0 },
-{"ble",	    "x,y,p",	0, (int) M_BLE, INSN_MACRO,	0,	0 },
-{"ble",     "x,8,p",	0, (int) M_BLE_I, INSN_MACRO,	0,	0 },
-{"bleu",    "x,y,p",	0, (int) M_BLEU, INSN_MACRO,	0,	0 },
-{"bleu",    "x,8,p",	0, (int) M_BLEU_I, INSN_MACRO,	0,	0 },
-{"blt",	    "x,y,p",	0, (int) M_BLT, INSN_MACRO,	0,	0 },
-{"blt",     "x,8,p",	0, (int) M_BLT_I, INSN_MACRO,	0,	0 },
-{"bltu",    "x,y,p",	0, (int) M_BLTU, INSN_MACRO,	0,	0 },
-{"bltu",    "x,8,p",	0, (int) M_BLTU_I, INSN_MACRO,	0,	0 },
-{"bne",	    "x,y,p",	0, (int) M_BNE, INSN_MACRO,	0,	0 },
-{"bne",     "x,U,p",	0, (int) M_BNE_I, INSN_MACRO,	0,	0 },
-{"bnez",    "x,p",	0x2800, 0xf800, BR|RD_x,	0,	0 },
-{"break",   "6",	0xe805, 0xf81f, TRAP,		0,	0 },
-{"bteqz",   "p",	0x6000, 0xff00, BR|RD_T,	0,	0 },
-{"btnez",   "p",	0x6100, 0xff00, BR|RD_T,	0,	0 },
-{"cmpi",    "x,U",	0x7000, 0xf800, WR_T|RD_x,	0,	0 },
-{"cmp",	    "x,y",	0xe80a, 0xf81f, WR_T|RD_x|RD_y,	0,	0 },
-{"cmp",     "x,U",	0x7000, 0xf800, WR_T|RD_x,	0,	0 },
+{"nop",	    "",		0x6500, 0xffff, RD_Z,		0,	I1 }, /* move $0,$Z */
+{"la",	    "x,A",	0x0800, 0xf800, WR_x|RD_PC,	0,	I1 },
+{"abs",	    "x,w",	0, (int) M_ABS, INSN_MACRO,	0,	I1 },
+{"addiu",   "y,x,4",	0x4000, 0xf810, WR_y|RD_x,	0,	I1 },
+{"addiu",   "x,k",	0x4800, 0xf800, WR_x|RD_x,	0,	I1 },
+{"addiu",   "S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	I1 },
+{"addiu",   "S,S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	I1 },
+{"addiu",   "x,P,V",	0x0800, 0xf800, WR_x|RD_PC,	0,	I1 },
+{"addiu",   "x,S,V",	0x0000, 0xf800, WR_x|RD_SP,	0,	I1 },
+{"addu",    "z,v,y",	0xe001, 0xf803, WR_z|RD_x|RD_y,	0,	I1 },
+{"addu",    "y,x,4",	0x4000, 0xf810, WR_y|RD_x,	0,	I1 },
+{"addu",    "x,k",	0x4800, 0xf800, WR_x|RD_x,	0,	I1 },
+{"addu",    "S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	I1 },
+{"addu",    "S,S,K",	0x6300, 0xff00, WR_SP|RD_SP,	0,	I1 },
+{"addu",    "x,P,V",	0x0800, 0xf800, WR_x|RD_PC,	0,	I1 },
+{"addu",    "x,S,V",	0x0000, 0xf800, WR_x|RD_SP,	0,	I1 },
+{"and",	    "x,y",	0xe80c, 0xf81f, WR_x|RD_x|RD_y,	0,	I1 },
+{"b",	    "q",	0x1000, 0xf800, BR,		0,	I1 },
+{"beq",	    "x,y,p",	0, (int) M_BEQ, INSN_MACRO,	0,	I1 },
+{"beq",     "x,U,p",	0, (int) M_BEQ_I, INSN_MACRO,	0,	I1 },
+{"beqz",    "x,p",	0x2000, 0xf800, BR|RD_x,	0,	I1 },
+{"bge",	    "x,y,p",	0, (int) M_BGE, INSN_MACRO,	0,	I1 },
+{"bge",     "x,8,p",	0, (int) M_BGE_I, INSN_MACRO,	0,	I1 },
+{"bgeu",    "x,y,p",	0, (int) M_BGEU, INSN_MACRO,	0,	I1 },
+{"bgeu",    "x,8,p",	0, (int) M_BGEU_I, INSN_MACRO,	0,	I1 },
+{"bgt",	    "x,y,p",	0, (int) M_BGT, INSN_MACRO,	0,	I1 },
+{"bgt",     "x,8,p",	0, (int) M_BGT_I, INSN_MACRO,	0,	I1 },
+{"bgtu",    "x,y,p",	0, (int) M_BGTU, INSN_MACRO,	0,	I1 },
+{"bgtu",    "x,8,p",	0, (int) M_BGTU_I, INSN_MACRO,	0,	I1 },
+{"ble",	    "x,y,p",	0, (int) M_BLE, INSN_MACRO,	0,	I1 },
+{"ble",     "x,8,p",	0, (int) M_BLE_I, INSN_MACRO,	0,	I1 },
+{"bleu",    "x,y,p",	0, (int) M_BLEU, INSN_MACRO,	0,	I1 },
+{"bleu",    "x,8,p",	0, (int) M_BLEU_I, INSN_MACRO,	0,	I1 },
+{"blt",	    "x,y,p",	0, (int) M_BLT, INSN_MACRO,	0,	I1 },
+{"blt",     "x,8,p",	0, (int) M_BLT_I, INSN_MACRO,	0,	I1 },
+{"bltu",    "x,y,p",	0, (int) M_BLTU, INSN_MACRO,	0,	I1 },
+{"bltu",    "x,8,p",	0, (int) M_BLTU_I, INSN_MACRO,	0,	I1 },
+{"bne",	    "x,y,p",	0, (int) M_BNE, INSN_MACRO,	0,	I1 },
+{"bne",     "x,U,p",	0, (int) M_BNE_I, INSN_MACRO,	0,	I1 },
+{"bnez",    "x,p",	0x2800, 0xf800, BR|RD_x,	0,	I1 },
+{"break",   "6",	0xe805, 0xf81f, TRAP,		0,	I1 },
+{"bteqz",   "p",	0x6000, 0xff00, BR|RD_T,	0,	I1 },
+{"btnez",   "p",	0x6100, 0xff00, BR|RD_T,	0,	I1 },
+{"cmpi",    "x,U",	0x7000, 0xf800, WR_T|RD_x,	0,	I1 },
+{"cmp",	    "x,y",	0xe80a, 0xf81f, WR_T|RD_x|RD_y,	0,	I1 },
+{"cmp",     "x,U",	0x7000, 0xf800, WR_T|RD_x,	0,	I1 },
 {"dla",	    "y,E",	0xfe00, 0xff00, WR_y|RD_PC, 	0,	I3 },
 {"daddiu",  "y,x,4",	0x4010, 0xf810, WR_y|RD_x, 	0,	I3 },
 {"daddiu",  "y,j",	0xfd00, 0xff00, WR_y|RD_y, 	0,	I3 },
@@ -126,20 +128,20 @@ const struct mips_opcode mips16_opcodes[] =
 {"daddu",   "y,P,W",	0xfe00, 0xff00, WR_y|RD_PC, 	0,	I3 },
 {"daddu",   "y,S,W",	0xff00, 0xff00, WR_y|RD_SP, 	0,	I3 },
 {"ddiv",    "0,x,y",	0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 	0,	I3 },
-{"ddiv",    "z,v,y",	0, (int) M_DDIV_3, INSN_MACRO,	0,	0 },
+{"ddiv",    "z,v,y",	0, (int) M_DDIV_3, INSN_MACRO,	0,	I1 },
 {"ddivu",   "0,x,y",	0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0,	I3 },
-{"ddivu",   "z,v,y",	0, (int) M_DDIVU_3, INSN_MACRO,	0,	0 },
-{"div",     "0,x,y",	0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	0 },
-{"div",     "z,v,y",	0, (int) M_DIV_3, INSN_MACRO,	0,	0 },
-{"divu",    "0,x,y",	0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	0 },
-{"divu",    "z,v,y",	0, (int) M_DIVU_3, INSN_MACRO,	0,	0 },
+{"ddivu",   "z,v,y",	0, (int) M_DDIVU_3, INSN_MACRO,	0,	I1 },
+{"div",     "0,x,y",	0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	I1 },
+{"div",     "z,v,y",	0, (int) M_DIV_3, INSN_MACRO,	0,	I1 },
+{"divu",    "0,x,y",	0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	I1 },
+{"divu",    "z,v,y",	0, (int) M_DIVU_3, INSN_MACRO,	0,	I1 },
 {"dmul",    "z,v,y",	0, (int) M_DMUL, INSN_MACRO, 	0,	I3 },
 {"dmult",   "x,y",	0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0,	I3 },
 {"dmultu",  "x,y",	0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0,	I3 },
 {"drem",    "0,x,y",	0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0,	I3 },
-{"drem",    "z,v,y",	0, (int) M_DREM_3, INSN_MACRO,	0,	0 },
+{"drem",    "z,v,y",	0, (int) M_DREM_3, INSN_MACRO,	0,	I1 },
 {"dremu",   "0,x,y",	0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0,	I3 },
-{"dremu",   "z,v,y",	0, (int) M_DREMU_3, INSN_MACRO,	0,	0 },
+{"dremu",   "z,v,y",	0, (int) M_DREMU_3, INSN_MACRO,	0,	I1 },
 {"dsllv",   "y,x",	0xe814, 0xf81f, WR_y|RD_y|RD_x, 0,	I3 },
 {"dsll",    "x,w,[",	0x3001, 0xf803, WR_x|RD_y, 	0,	I3 },
 {"dsll",    "y,x",	0xe814, 0xf81f, WR_y|RD_y|RD_x, 0,	I3 },
@@ -150,92 +152,92 @@ const struct mips_opcode mips16_opcodes[] =
 {"dsrl",    "y,]",	0xe808, 0xf81f, WR_y|RD_y, 	0,	I3 },
 {"dsrl",    "y,x",	0xe816, 0xf81f, WR_y|RD_y|RD_x, 0,	I3 },
 {"dsubu",   "z,v,y",	0xe002, 0xf803, WR_z|RD_x|RD_y, 0,	I3 },
-{"dsubu",   "y,x,4",	0, (int) M_DSUBU_I, INSN_MACRO,	0,	0 },
-{"dsubu",   "y,j",	0, (int) M_DSUBU_I_2, INSN_MACRO, 0,	0 },
-{"exit",    "L",	0xed09, 0xff1f, TRAP,		0,	0 },
-{"exit",    "L",	0xee09, 0xff1f, TRAP,		0,	0 },
-{"exit",    "L",	0xef09, 0xff1f, TRAP,		0,	0 },
-{"entry",   "l",	0xe809, 0xf81f, TRAP,		0,	0 },
-{"extend",  "e",	0xf000, 0xf800, 0,		0,	0 },
-{"jalr",    "x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	0 },
-{"jalr",    "R,x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	0 },
-{"jal",     "x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	0 },
-{"jal",     "R,x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	0 },
-{"jal",	    "a",	0x1800, 0xfc00, UBD|WR_31,	0,	0 },
-{"jalx",    "a",	0x1c00, 0xfc00, UBD|WR_31,	0,	0 },
-{"jr",	    "x",	0xe800, 0xf8ff, UBD|RD_x,	0,	0 },
-{"jr",	    "R",	0xe820, 0xffff, UBD|RD_31,	0,	0 },
-{"j",	    "x",	0xe800, 0xf8ff, UBD|RD_x,	0,	0 },
-{"j",	    "R",	0xe820, 0xffff, UBD|RD_31,	0,	0 },
-{"lb",	    "y,5(x)",	0x8000, 0xf800, WR_y|RD_x,	0,	0 },
-{"lbu",	    "y,5(x)",	0xa000, 0xf800, WR_y|RD_x,	0,	0 },
+{"dsubu",   "y,x,4",	0, (int) M_DSUBU_I, INSN_MACRO,	0,	I1 },
+{"dsubu",   "y,j",	0, (int) M_DSUBU_I_2, INSN_MACRO, 0,	I1 },
+{"exit",    "L",	0xed09, 0xff1f, TRAP,		0,	I1 },
+{"exit",    "L",	0xee09, 0xff1f, TRAP,		0,	I1 },
+{"exit",    "L",	0xef09, 0xff1f, TRAP,		0,	I1 },
+{"entry",   "l",	0xe809, 0xf81f, TRAP,		0,	I1 },
+{"extend",  "e",	0xf000, 0xf800, 0,		0,	I1 },
+{"jalr",    "x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	I1 },
+{"jalr",    "R,x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	I1 },
+{"jal",     "x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	I1 },
+{"jal",     "R,x",	0xe840, 0xf8ff, UBD|WR_31|RD_x,	0,	I1 },
+{"jal",	    "a",	0x1800, 0xfc00, UBD|WR_31,	0,	I1 },
+{"jalx",    "a",	0x1c00, 0xfc00, UBD|WR_31,	0,	I1 },
+{"jr",	    "x",	0xe800, 0xf8ff, UBD|RD_x,	0,	I1 },
+{"jr",	    "R",	0xe820, 0xffff, UBD|RD_31,	0,	I1 },
+{"j",	    "x",	0xe800, 0xf8ff, UBD|RD_x,	0,	I1 },
+{"j",	    "R",	0xe820, 0xffff, UBD|RD_31,	0,	I1 },
+{"lb",	    "y,5(x)",	0x8000, 0xf800, WR_y|RD_x,	0,	I1 },
+{"lbu",	    "y,5(x)",	0xa000, 0xf800, WR_y|RD_x,	0,	I1 },
 {"ld",	    "y,D(x)",	0x3800, 0xf800, WR_y|RD_x, 	0,	I3 },
 {"ld",	    "y,B",	0xfc00, 0xff00, WR_y|RD_PC, 	0,	I3 },
 {"ld",	    "y,D(P)",	0xfc00, 0xff00, WR_y|RD_PC, 	0,	I3 },
 {"ld",	    "y,D(S)",	0xf800, 0xff00, WR_y|RD_SP, 	0,	I3 },
-{"lh",	    "y,H(x)",	0x8800, 0xf800, WR_y|RD_x,	0,	0 },
-{"lhu",	    "y,H(x)",	0xa800, 0xf800, WR_y|RD_x,	0,	0 },
-{"li",	    "x,U",	0x6800, 0xf800, WR_x,		0,	0 },
-{"lw",	    "y,W(x)",	0x9800, 0xf800, WR_y|RD_x,	0,	0 },
-{"lw",	    "x,A",	0xb000, 0xf800, WR_x|RD_PC,	0,	0 },
-{"lw",	    "x,V(P)",	0xb000, 0xf800, WR_x|RD_PC,	0,	0 },
-{"lw",	    "x,V(S)",	0x9000, 0xf800, WR_x|RD_SP,	0,	0 },
+{"lh",	    "y,H(x)",	0x8800, 0xf800, WR_y|RD_x,	0,	I1 },
+{"lhu",	    "y,H(x)",	0xa800, 0xf800, WR_y|RD_x,	0,	I1 },
+{"li",	    "x,U",	0x6800, 0xf800, WR_x,		0,	I1 },
+{"lw",	    "y,W(x)",	0x9800, 0xf800, WR_y|RD_x,	0,	I1 },
+{"lw",	    "x,A",	0xb000, 0xf800, WR_x|RD_PC,	0,	I1 },
+{"lw",	    "x,V(P)",	0xb000, 0xf800, WR_x|RD_PC,	0,	I1 },
+{"lw",	    "x,V(S)",	0x9000, 0xf800, WR_x|RD_SP,	0,	I1 },
 {"lwu",     "y,W(x)",	0xb800, 0xf800, WR_y|RD_x, 	0,	I3 },
-{"mfhi",    "x",	0xe810, 0xf8ff, WR_x|RD_HI,	0,	0 },
-{"mflo",    "x",	0xe812, 0xf8ff, WR_x|RD_LO,	0,	0 },
-{"move",    "y,X",	0x6700, 0xff00, WR_y|RD_X, 	0,	0 },
-{"move",    "Y,Z",	0x6500, 0xff00, WR_Y|RD_Z,	0,	0 },
-{"mul",     "z,v,y",	0, (int) M_MUL, INSN_MACRO,	0,	0 },
-{"mult",    "x,y",	0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	0 },
-{"multu",   "x,y",	0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	0 },
-{"neg",	    "x,w",	0xe80b, 0xf81f, WR_x|RD_y,	0,	0 },
-{"not",	    "x,w",	0xe80f, 0xf81f, WR_x|RD_y,	0,	0 },
-{"or",	    "x,y",	0xe80d, 0xf81f, WR_x|RD_x|RD_y,	0,	0 },
-{"rem",     "0,x,y",	0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	0 },
-{"rem",     "z,v,y",	0, (int) M_REM_3, INSN_MACRO,	0,	0 },
-{"remu",    "0,x,y",	0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	0 },
-{"remu",    "z,v,y",	0, (int) M_REMU_3, INSN_MACRO,	0,	0 },
-{"sb",	    "y,5(x)",	0xc000, 0xf800, RD_y|RD_x,	0,	0 },
+{"mfhi",    "x",	0xe810, 0xf8ff, WR_x|RD_HI,	0,	I1 },
+{"mflo",    "x",	0xe812, 0xf8ff, WR_x|RD_LO,	0,	I1 },
+{"move",    "y,X",	0x6700, 0xff00, WR_y|RD_X, 	0,	I1 },
+{"move",    "Y,Z",	0x6500, 0xff00, WR_Y|RD_Z,	0,	I1 },
+{"mul",     "z,v,y",	0, (int) M_MUL, INSN_MACRO,	0,	I1 },
+{"mult",    "x,y",	0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	I1 },
+{"multu",   "x,y",	0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	I1 },
+{"neg",	    "x,w",	0xe80b, 0xf81f, WR_x|RD_y,	0,	I1 },
+{"not",	    "x,w",	0xe80f, 0xf81f, WR_x|RD_y,	0,	I1 },
+{"or",	    "x,y",	0xe80d, 0xf81f, WR_x|RD_x|RD_y,	0,	I1 },
+{"rem",     "0,x,y",	0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	I1 },
+{"rem",     "z,v,y",	0, (int) M_REM_3, INSN_MACRO,	0,	I1 },
+{"remu",    "0,x,y",	0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO,	0,	I1 },
+{"remu",    "z,v,y",	0, (int) M_REMU_3, INSN_MACRO,	0,	I1 },
+{"sb",	    "y,5(x)",	0xc000, 0xf800, RD_y|RD_x,	0,	I1 },
 {"sd",	    "y,D(x)",	0x7800, 0xf800, RD_y|RD_x, 	0,	I3 },
 {"sd",	    "y,D(S)",	0xf900, 0xff00, RD_y|RD_PC, 	0,	I3 },
-{"sd",	    "R,C(S)",	0xfa00, 0xff00, RD_31|RD_PC,	0,	0 },
-{"sh",	    "y,H(x)",	0xc800, 0xf800, RD_y|RD_x,	0,	0 },
-{"sllv",    "y,x",	0xe804, 0xf81f, WR_y|RD_y|RD_x, 0,	0 },
-{"sll",	    "x,w,<",	0x3000, 0xf803, WR_x|RD_y,	0,	0 },
-{"sll",     "y,x",	0xe804, 0xf81f, WR_y|RD_y|RD_x,	0,	0 },
-{"slti",    "x,8",	0x5000, 0xf800, WR_T|RD_x,	0,	0 },
-{"slt",	    "x,y",	0xe802, 0xf81f, WR_T|RD_x|RD_y,	0,	0 },
-{"slt",     "x,8",	0x5000, 0xf800, WR_T|RD_x,	0,	0 },
-{"sltiu",   "x,8",	0x5800, 0xf800, WR_T|RD_x,	0,	0 },
-{"sltu",    "x,y",	0xe803, 0xf81f, WR_T|RD_x|RD_y,	0,	0 },
-{"sltu",    "x,8",	0x5800, 0xf800, WR_T|RD_x,	0,	0 },
-{"srav",    "y,x",	0xe807, 0xf81f, WR_y|RD_y|RD_x,	0,	0 },
-{"sra",	    "x,w,<",	0x3003, 0xf803, WR_x|RD_y,	0,	0 },
-{"sra",     "y,x",	0xe807, 0xf81f, WR_y|RD_y|RD_x,	0,	0 },
-{"srlv",    "y,x",	0xe806, 0xf81f, WR_y|RD_y|RD_x,	0,	0 },
-{"srl",	    "x,w,<",	0x3002, 0xf803, WR_x|RD_y,	0,	0 },
-{"srl",     "y,x",	0xe806, 0xf81f, WR_y|RD_y|RD_x,	0,	0 },
-{"subu",    "z,v,y",	0xe003, 0xf803, WR_z|RD_x|RD_y,	0,	0 },
-{"subu",    "y,x,4",	0, (int) M_SUBU_I, INSN_MACRO,	0,	0 },
-{"subu",    "x,k",	0, (int) M_SUBU_I_2, INSN_MACRO,0,	0 },
-{"sw",	    "y,W(x)",	0xd800, 0xf800, RD_y|RD_x,	0,	0 },
-{"sw",	    "x,V(S)",	0xd000, 0xf800, RD_x|RD_SP,	0,	0 },
-{"sw",	    "R,V(S)",	0x6200, 0xff00, RD_31|RD_SP,	0,	0 },
-{"xor",	    "x,y",	0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0,	0 },
+{"sd",	    "R,C(S)",	0xfa00, 0xff00, RD_31|RD_PC,	0,	I1 },
+{"sh",	    "y,H(x)",	0xc800, 0xf800, RD_y|RD_x,	0,	I1 },
+{"sllv",    "y,x",	0xe804, 0xf81f, WR_y|RD_y|RD_x, 0,	I1 },
+{"sll",	    "x,w,<",	0x3000, 0xf803, WR_x|RD_y,	0,	I1 },
+{"sll",     "y,x",	0xe804, 0xf81f, WR_y|RD_y|RD_x,	0,	I1 },
+{"slti",    "x,8",	0x5000, 0xf800, WR_T|RD_x,	0,	I1 },
+{"slt",	    "x,y",	0xe802, 0xf81f, WR_T|RD_x|RD_y,	0,	I1 },
+{"slt",     "x,8",	0x5000, 0xf800, WR_T|RD_x,	0,	I1 },
+{"sltiu",   "x,8",	0x5800, 0xf800, WR_T|RD_x,	0,	I1 },
+{"sltu",    "x,y",	0xe803, 0xf81f, WR_T|RD_x|RD_y,	0,	I1 },
+{"sltu",    "x,8",	0x5800, 0xf800, WR_T|RD_x,	0,	I1 },
+{"srav",    "y,x",	0xe807, 0xf81f, WR_y|RD_y|RD_x,	0,	I1 },
+{"sra",	    "x,w,<",	0x3003, 0xf803, WR_x|RD_y,	0,	I1 },
+{"sra",     "y,x",	0xe807, 0xf81f, WR_y|RD_y|RD_x,	0,	I1 },
+{"srlv",    "y,x",	0xe806, 0xf81f, WR_y|RD_y|RD_x,	0,	I1 },
+{"srl",	    "x,w,<",	0x3002, 0xf803, WR_x|RD_y,	0,	I1 },
+{"srl",     "y,x",	0xe806, 0xf81f, WR_y|RD_y|RD_x,	0,	I1 },
+{"subu",    "z,v,y",	0xe003, 0xf803, WR_z|RD_x|RD_y,	0,	I1 },
+{"subu",    "y,x,4",	0, (int) M_SUBU_I, INSN_MACRO,	0,	I1 },
+{"subu",    "x,k",	0, (int) M_SUBU_I_2, INSN_MACRO,0,	I1 },
+{"sw",	    "y,W(x)",	0xd800, 0xf800, RD_y|RD_x,	0,	I1 },
+{"sw",	    "x,V(S)",	0xd000, 0xf800, RD_x|RD_SP,	0,	I1 },
+{"sw",	    "R,V(S)",	0x6200, 0xff00, RD_31|RD_SP,	0,	I1 },
+{"xor",	    "x,y",	0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0,	I1 },
   /* MIPS16e additions */
-{"jalrc",   "x",	0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     0 },
-{"jalrc",   "R,x",	0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     0 },
-{"jrc",     "x",	0xe880, 0xf8ff, RD_x|TRAP,	0,      0 },
-{"jrc",     "R",	0xe8a0, 0xffff, RD_31|TRAP,	0,      0 },
-{"restore", "M",	0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP,	0,	0 },
-{"save",    "m",	0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP,	0,	0 },
-{"sdbbp",   "6",	0xe801, 0xf81f, TRAP,		0,	0 },
-{"seb",	    "x",	0xe891, 0xf8ff, WR_x|RD_x,	0,      0 },
-{"seh",	    "x",	0xe8b1, 0xf8ff, WR_x|RD_x,	0,      0 },
-{"sew",	    "x",	0xe8d1, 0xf8ff, WR_x|RD_x,	0,      I3 },
-{"zeb",	    "x",	0xe811, 0xf8ff, WR_x|RD_x,	0,      0 },
-{"zeh",	    "x",	0xe831, 0xf8ff, WR_x|RD_x,	0,      0 },
-{"zew",	    "x",	0xe851, 0xf8ff, WR_x|RD_x,	0,      I3 },
+{"jalrc",   "x",	0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     I32 },
+{"jalrc",   "R,x",	0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     I32 },
+{"jrc",     "x",	0xe880, 0xf8ff, RD_x|TRAP,	0,      I32 },
+{"jrc",     "R",	0xe8a0, 0xffff, RD_31|TRAP,	0,      I32 },
+{"restore", "M",	0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP,	0,	I32 },
+{"save",    "m",	0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP,	0,	I32 },
+{"sdbbp",   "6",	0xe801, 0xf81f, TRAP,		0,	I32 },
+{"seb",	    "x",	0xe891, 0xf8ff, WR_x|RD_x,	0,      I32 },
+{"seh",	    "x",	0xe8b1, 0xf8ff, WR_x|RD_x,	0,      I32 },
+{"sew",	    "x",	0xe8d1, 0xf8ff, WR_x|RD_x,	0,      I64 },
+{"zeb",	    "x",	0xe811, 0xf8ff, WR_x|RD_x,	0,      I32 },
+{"zeh",	    "x",	0xe831, 0xf8ff, WR_x|RD_x,	0,      I32 },
+{"zew",	    "x",	0xe851, 0xf8ff, WR_x|RD_x,	0,      I64 },
 };
 
 const int bfd_mips16_num_opcodes =